參數(shù)資料
型號: AD9992BBCZRL
廠商: Analog Devices Inc
文件頁數(shù): 31/92頁
文件大?。?/td> 0K
描述: IC CCD SGNL PROC 12BIT 105CSPBGA
產(chǎn)品變化通告: AD9992 Discontinuation 22/Feb/2012
標(biāo)準(zhǔn)包裝: 2,000
類型: CCD 信號處理器,12 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
電流 - 電源: 27mA
安裝類型: 表面貼裝
封裝/外殼: 105-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 105-CSPBGA(8x8)
包裝: 帶卷 (TR)
AD9992
Rev. C | Page 37 of 92
Hold Area Using FREEZE/RESUME Registers
The FREEZE/RESUME registers can also be used to create a
hold area in which the V-outputs are temporarily held and later
continued, starting at the point where they were held. As shown
in Figure 45, this is different from the VMASK_EN register
because the V-outputs continue from where they stopped rather
than from where they would have been. The hold area
temporarily stops the pixel counter for the V-outputs, while the
V-masking allows the counter to continue in the masking area.
XV1
XV8
HD
NOTES
1. WHEN HOLD = 1 FOR ANY V-SEQUENCE GROUP, THE FREEZE AND RESUME REGISTERS ARE USED TO SPECIFY THE HOLD AREA.
2. ABOVE EXAMPLE: XV1 TO XV10 ARE ASSIGNED TO GROUP A. HOLD BIT FOR GROUP A = 1.
3. H-COUNTER FOR GROUP A (XV1 TO XV10) STOPS DURING HOLD AREA.
XV9
HOLD AREA
FOR GROUP A
XV10
FREEZE
RESUME
0
58
91
-04
5
Figure 45. Hold Area for Group A
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