tOD NOTES 1. D" />
參數(shù)資料
型號(hào): AD9992BBCZRL
廠商: Analog Devices Inc
文件頁數(shù): 10/92頁
文件大?。?/td> 0K
描述: IC CCD SGNL PROC 12BIT 105CSPBGA
產(chǎn)品變化通告: AD9992 Discontinuation 22/Feb/2012
標(biāo)準(zhǔn)包裝: 2,000
類型: CCD 信號(hào)處理器,12 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
電流 - 電源: 27mA
安裝類型: 表面貼裝
封裝/外殼: 105-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 105-CSPBGA(8x8)
包裝: 帶卷 (TR)
AD9992
Rev. C | Page 18 of 92
P[0]
P[64] = P[0]
PIXEL
PERIOD
P[16]
P[32]
P[48]
DOUT
DCLK
tOD
NOTES
1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 64 DIFFERENT LOCATIONS.
3. DCLK CAN BE INVERTED WITH RESPECT TO DOUT BY USING THE DCLKINV REGISTER.
05
89
1-
02
0
Figure 20. Digital Output Phase Adjustment Using DOUTPHASEP Register
NOTES
1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.
2. HIGHER VALUES OF SHD AND/OR DOUT PHASE SHIFTS DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
3. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE SHPLOC OR UP TO 15 EDGES FOLLOWING SHPLOC.
DCLK
DOUT
CCDIN
CLI
SHD
(INTERNAL)
ADC DOUT
(INTERNAL)
NN + 2
N + 1
N + 3
N + 13
N + 12
N + 11
N + 10
N + 9
N + 8
N + 7
N + 6
N + 5
N + 4
N + 14
SAMPLE PIXEL N
N + 16
N + 17
N + 15
N – 14
N – 4
N – 5
N – 6
N – 7
N – 8
N – 9
N – 10
N – 11
N – 12
N – 13
N – 3
N – 2
N – 1
N
N + 1
N – 15
N – 16
N – 17
tCLIDLY
PIPELINE LATENCY = 16 CYCLES
N – 14
N – 4
N – 5
N – 6
N – 7
N – 8
N – 9
N – 10
N – 11
N – 12
N – 13
N – 3
N – 2
N – 1
N
N + 1
N – 15
N – 16
N – 17
tDOUTINH
05891-
021
Figure 21. Digital Data Output Pipeline Delay
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