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| 型號(hào)： | AD9992BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/92頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號(hào)處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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12-Bit CCD Signal Processor with
Precision Timing Generator
AD9992
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006–2007 Analog Devices, Inc. All rights reserved.
FEATURES
1.8 V AFETG core
Internal LDO regulator and charge pump circuitry
Compatibility with 3 V or 1.8 V systems
24 programmable vertical clock outputs
Correlated double sampler (CDS) with 3 dB, 0 dB,
+3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
12-bit, 40 MHz ADC
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip driver for external crystal
On-chip sync generator with external sync input
105-lead CSP_BGA package, 8 mm × 8 mm, 0.65 mm pitch
APPLICATIONS
Digital still cameras
GENERAL DESCRIPTION
The AD9992 is a highly integrated CCD signal processor for
digital still camera applications. It includes a complete analog
front end with analog to digital conversion combined with
a full-function programmable timing generator. The timing
generator is capable of supporting up to 24 vertical clock signals
to control advanced CCDs. A Precision Timing core allows
adjustment of high speed clocks with approximately 400 ps
resolution at 40 MHz operation. The AD9992 also contains
eight general-purpose inputs/outputs that can be used for
shutter and system functions.
The AD9992 is specified at pixel rates of up to 40 MHz. The
analog front end includes black level clamping, CDS, VGA, and
a 12-bit analog-to-digital converter (ADC). The timing generator
provides all the necessary CCD clocks: RG, H-clocks, V-clocks,
sensor gate pulses, substrate clock, and substrate bias control.
Operation is programmed using a 3-wire serial interface.
The AD9992 is specified over an operating temperature range
of 25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
AD9992
CDS
VGA
CLAMP
12-BIT
ADC
SL
SCK
SDATA
CLI
DOUT
VREF
6dB TO 42dB
HORIZONTAL
DRIVERS
VERTICAL
TIMING
CONTROL
RG
H1 TO H8
24
REFT REFB
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL CLOCKS
HD
VD SYNC
INTERNAL
REGISTERS
CCDIN
–3dB, 0dB, +3dB, +6dB
12
HL
CLO
GPO1 TO GPO8
XV1 TO XV24
XSUBCK
3V OUTPUT
1.8V INPUT
8
CHARGE
PUMP
1.8V OUTPUT
3V INPUT
LDO
REG
05
89
1-
00
1
Figure 1.
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