參數(shù)資料
型號(hào)： A48P3616
廠商： AMIC Technology Corporation
英文描述： CAP 270PF 50V CERAMIC MONO 5%
中文描述： 8米× 16位DDR內(nèi)存
文件頁(yè)數(shù)： 5/62頁(yè)
文件大小： 2214K
代理商： A48P3616
Preliminary
A48P3616
8M X 16 Bit DDR DRAM
Preliminary (September 2005, Version 0.0)
4
AMIC Technology, Corp.
Input/Output Functional Description
Symbol
Type
Function
CK,
CK
Input
Clock:
CK and
CK
are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of
CK
. Output
(read) data is referenced to the crossings of CK and
CK
(both directions of crossing).
CKE, CKE1, CKE1
Input
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power Down
and Self Refresh operation (all banks idle), or Active Power Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is
asynchronous for self refresh exit. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK,
CK
and CKE are disabled during Power Down.
Input buffers, excluding CKE, are disabled during self refresh. The standard pinout includes
one CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0,
to facilitate independent power down control of stacked devices.
CS
,
CS0
,
CS1
Input
Chip Select:
All commands are masked when
CS
is registered high.
CS
provides for
external bank selection on systems with multiple banks.
CS
is considered part of the
command code. The standard pinout includes one
CS
pin. Optional pinouts might include
CS1
on a different pin, in addition to
CS0
, to allow upper or lower deck selection on
stacked devices.
RAS
,
CAS
,
WE
Input
Command Inputs:
RAS
,
CAS
and
WE
(along with
CS
) define the command being
entered.
DM
Input
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM
is sampled high coincident with that input data during a Write access. DM is sampled on
both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and
DQS loading. During a Read, DM can be driven high, low, or floated.
BA0, BA1
Input
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. BA0 and BA1 also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provide the row address for Active commands, and the column address
and Auto Precharge bit for Read/Write commands, to select one location out of the memory
array in the respective bank. A10 is sampled during a Precharge command to determine
whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one
bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a Mode Register Set command.
A0 – A11
Input
DQ
Input/Output
Data Input/Output:
Data bus.
DQS, LDQS, UDQS Input/Output
Data Strobe:
Output with read data, input with write data. Edge-aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to the
data on DQ0- DQ7; UDQS corresponds to the data on DQ8-DQ15
NC
No Connect:
No internal electrical connection is present.
NU
Electrical connection is present. Should not be connected at second level of assembly.
VDDQ
Supply
DQ Power Supply:
2.5V
±
0.2V.
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply:
2.5V
±
0.2V.
VSS
Supply
Ground
VREF
Supply
SSTL_2 reference voltage:
(V
DDQ
/ 2)
±
1%.
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A-48P36G 制造商:Pentair Technical Products / Hoffman 功能描述:PANEL, ENCLOSURE, 45INX33IN, STEEL, Panel Material:Steel, Body Color:-, For Use With:NEMA 3R, 4, 4X, 12 , and 13 Enclosures, External Height - Imperial:45", External Height - Metric:1143mm, External Width - Imperial:33" , RoHS Compliant: Yes 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:PANEL, ENCLOSURE, 45INX33IN, STEEL, Panel Material:Steel, Body Color:(Not Applic
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