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參數資料
| 型號： | A48P3616 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAP 270PF 50V CERAMIC MONO 5% |
| 中文描述： | 8米× 16位DDR內存 |
| 文件頁數： | 2/62頁 |
| 文件大?。?/td> | 2214K |
| 代理商： | A48P3616 |
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Preliminary
A48P3616
8M X 16 Bit DDR DRAM
Preliminary (September 2005, Version 0.0)
1
AMIC Technology, Corp.
Feature
CAS Latency and Frequency
Maximum Operating Frequency (MHz)
DDR466
(43)
(5T)
-
-
-
166
233
200
CAS
Latency
DDR400
DDR333
(6K)
133
166
-
DDR266
(75B)
100
133
-
2
2.5
3
Double data rate architecture: two data transfers per clock
cycle.
Bidirectional data strobe (DQS) is transmitted and received
with data, to be used in capturing data at the receiver.
DQS is edge-aligned with data for reads and is center-
aligned with data for writes.
Differential clock inputs (CK andCK )
Four internal banks for concurrent operation
Data mask (DM) for write data.
DLL aligns DQ and DQS transitions with CK transitions.
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS.
Burst lengths: 2, 4, or 8
CAS Latency: 2 & 2.5 for 6K/75B, 2.5 & 3 for 5T, 3 for 43
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
15.6μs Maximum Average Periodic Refresh Interval
2.5V (SSTL_2 compatible) I/O
V
DD
= V
DDQ
= 2.5V
±
0.2V (6K/75B)
V
DD
= V
DDQ
= 2.6V
±
0.1V (5T/43)
Lead-free and Halogen-free product available
General Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 134,217,728 bits. It is
internally configured as a quad-bank DRAM and is based on
Nanya’s 110nm process.
The 128Mb DDR SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the 128Mb DDR SDRAM effectively consists of a single 2n-bit
wide, one clock cycle data transfer at the internal DRAM core
and two corresponding n-bit wide, one-half-clock-cycle data
transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads and
by the memory controller during Writes. DQS is edgealigned
with data for Reads and center-aligned with data for Writes.
The 128Mb DDR SDRAM operates from a differential clock
(CK and CK ; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence.
Accesses begin with the registration of an Active command,
which is then followed by a Read or Write command. The
address bits registered coincident with the Active command
are used to select the bank and row to be accessed. The
address bits registered coincident with the Read or Write
command are used to select the bank and the starting column
location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank
architecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row
precharge and activation time.
An auto refresh mode is provided along with a power-saving
Power Down mode.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| A48P36AL | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 45.00x33.00 fits 48.00x3 , fits 48x36, Aluminum |
| A-48P36AL | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 45.00x33.00 fits 48.00x3 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:Panel 45.00x33.00 fits 48.00x3 |
| A48P36G | 制造商:Pentair Technical Products / Hoffman 功能描述:Enclosure, Panel, 1.25x33.25x45.75 |
| A-48P36G | 制造商:Pentair Technical Products / Hoffman 功能描述:PANEL, ENCLOSURE, 45INX33IN, STEEL, Panel Material:Steel, Body Color:-, For Use With:NEMA 3R, 4, 4X, 12 , and 13 Enclosures, External Height - Imperial:45", External Height - Metric:1143mm, External Width - Imperial:33" , RoHS Compliant: Yes 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:PANEL, ENCLOSURE, 45INX33IN, STEEL, Panel Material:Steel, Body Color:(Not Applic |
| A48P36SS6 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 45.00x33.00 fits 48.00x3 , fits 48x36, SS Type 316 |
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