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參數資料
| 型號： | A48P3616 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | CAP 270PF 50V CERAMIC MONO 5% |
| 中文描述： | 8米× 16位DDR內存 |
| 文件頁數： | 21/62頁 |
| 文件大?。?/td> | 2214K |
| 代理商： | A48P3616 |
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Preliminary
A48P3616
8M X 16 Bit DDR DRAM
Preliminary (September 2005, Version 0.0)
20
AMIC Technology, Corp.
Auto Refresh
Auto Refresh is used during normal operation of the DDR
SDRAM and is analogous to CAS Before RAS (CBR)
Refresh in previous DRAM types. This command is
nonpersistent, so it must be issued each time a refresh is
required.
The refresh addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during an
Auto Refresh command. The 128Mb DDR SDRAM requires
Auto Refresh cycles at an average periodic interval of 7.8μs
(maximum).
Self Refresh
The Self Refresh command can be used to retain data in the
DDR SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the DDR SDRAM retains data
without external clocking. The Self Refresh command is
initiated as an Auto Refresh command coincident with CKE
transitioning low. The DLL is automatically disabled upon
entering Self Refresh, and is automatically enabled upon
exiting Self Refresh (200 clock cycles must then occur before
a Read command can be issued). Input signals except CKE
(low) are “Don’t Care” during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of
commands. CK (and CK ) must be stable prior to CKE
returning high. Once CKE is high, the SDRAM must have
NOP commands issued for t
XSNR
because time is required for
the completion of any internal refresh in progress. A simple
algorithm for meeting both refresh and DLL requirements is to
apply NOPs for 200 clock cycles before applying any other
command.
Bank/Row Activation
Before any Read or Write commands can be issued to a bank
within the DDR SDRAM, a row in that bank must be “opened”
(activated). This is accomplished via the Active command and
addresses A0-A11, BA0 and BA1 (see Activating a Specific
Row in a Specific Bank), which decode and select both the
bank and the row to be activated. After opening a row (issuing
an Active command), a Read or Write command may be
issued to that row, subject to the t
RCD
specification. A
subsequent Active command to a different row in the same
bank can only be issued after the previous active row has
been “closed” (precharged). The minimum time interval
between successive Active commands to the same bank is
defined by t
RC
. A subsequent Active command to another
bank can be issued while the first bank is being accessed,
which results in a reduction of total row-access overhead. The
minimum time interval between successive Active commands
to different banks is defined by t
RRD
.
Reads
Subsequent to programming the mode register with CAS
latency, burst type, and burst length, Read bursts are initiated
with a Read command.
The starting column and bank addresses are provided with
the Read command and Auto Precharge is either enabled or
disabled for that burst access. If Auto Precharge is enabled,
the row that is accessed starts precharge at the completion of
the burst, provided t
RAS
has been satisfied. For the generic
Read commands used in the following illustrations, Auto
Precharge is disabled.
During Read bursts, the valid data-out element from the
starting column address is available following the CAS
latency after the Read command. Each subsequent data-out
element is valid nominally at the next positive or negative
clock edge (i.e. at the next crossing of CK and CK ). The
following timing figure entitled “Read Burst: CAS Latencies
(Burst Length=4)” illustrates the general timing for each
supported CAS latency setting. DQS is driven by the DDR
SDRAM along with output data. The initial low state on DQS
is known as the read preamble; the low state coincident with
the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands
have been initiated, the DQs and DQS goes High-Z. Data
from any Read burst may be concatenated with or truncated
with data from a subsequent Read command. In either case,
a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of
a completed burst or the last desired data element of a longer
burst which is being truncated. The new Read command
should be issued x cycles after the first Read command,
where x equals the number of desired data element pairs
(pairs are required by the 2n prefetch architecture). This is
shown in timing figure entitled “Consecutive Read Bursts:
CAS Latencies (Burst Length =4 or 8)”. A Read command can
be initiated on any positive clock cycle following a previous
Read command. Nonconsecutive Read data is shown in
timing figure entitled “Non-Consecutive Read Bursts: CAS
Latencies (Burst Length = 4)”. Full-speed Random Read
Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a
page (or pages) can be performed as shown on page 34.
CAS Latencies
Data from any Read burst may be truncated with a Burst
Terminate command, as shown in timing figure entitled
Terminating a Read Burst: CAS Latencies (Burst Length = 8)
on page 35. The Burst Terminate latency is equal to the read
(CAS) latency, i.e. the Burst Terminate command should be
issued x cycles after the Read command, where x equals the
number of desired data element pairs.
Data from any Read burst must be completed or truncated
before a subsequent Write command can be issued. If
truncation is necessary, the Burst Terminate command must
be used, as shown in timing figure entitled Read to Write:
CAS Latencies (Burst Length = 4 or 8) on page 36. The
example is shown for t
DQSS(min)
. The t
DQSS(max)
case, not
shown here, has a longer bus idle time. t
DQSS(min)
and t
DQSS(max)
are defined in the section on Writes.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| A48P36AL | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 45.00x33.00 fits 48.00x3 , fits 48x36, Aluminum |
| A-48P36AL | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 45.00x33.00 fits 48.00x3 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:Panel 45.00x33.00 fits 48.00x3 |
| A48P36G | 制造商:Pentair Technical Products / Hoffman 功能描述:Enclosure, Panel, 1.25x33.25x45.75 |
| A-48P36G | 制造商:Pentair Technical Products / Hoffman 功能描述:PANEL, ENCLOSURE, 45INX33IN, STEEL, Panel Material:Steel, Body Color:-, For Use With:NEMA 3R, 4, 4X, 12 , and 13 Enclosures, External Height - Imperial:45", External Height - Metric:1143mm, External Width - Imperial:33" , RoHS Compliant: Yes 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:PANEL, ENCLOSURE, 45INX33IN, STEEL, Panel Material:Steel, Body Color:(Not Applic |
| A48P36SS6 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 45.00x33.00 fits 48.00x3 , fits 48x36, SS Type 316 |
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