參數(shù)資料
型號： A48P3616
廠商： AMIC Technology Corporation
英文描述： CAP 270PF 50V CERAMIC MONO 5%
中文描述： 8米× 16位DDR內(nèi)存
文件頁數(shù)： 12/62頁
文件大?。?/td> 2214K
代理商： A48P3616
Preliminary
A48P3616
8M X 16 Bit DDR DRAM
Preliminary (September 2005, Version 0.0)
11
AMIC Technology, Corp.
I
DD
Specifications and Conditions
(0 °C
≤
T
A
≤
70
°
C
;
V
DD
= V
DDQ
= 2.5V
±
0.2V(6K/75B); V
DD
= V
DDQ
= 2.6V
±
0.1V (5T/43), See AC Characteristics)
Symbol
Parameter/Condition
DDR266
(75B)
tck = 6ns
DDR333
(6K)
tCK = 6ns
DDR400
(5T)
tCK = 5.0ns
DDR466
(43)
tCK = 4.3ns
Unit
Note
I
DD0
Operating Current
:
One bank; active / precharge; t
RC
= t
RC (min)
; DQ,
DM, and DQS inputs changing twice per clock
cycle; address and control inputs changing once
per clock cycle
Operating Current
:
One bank; active / read / precharge; Burst = 2; t
RC
= t
RC (min)
; CL = 2.5; I
OUT
= 0mA; address and
control inputs changing once per clock cycle
Precharge Power Down Standby Current
:
All banks idle; Power Down mode; CKE
≤
V
IL (max)
Idle Standby Current:
CS
≥
V
IH (min)
; all banks idle; CKE
≥
V
IH (min)
;
address and control inputs changing once per
clock cycle
Active Power Down Standby Current
: one bank
active; Power Down mode; CKE
≤
V
IL (max)
Active Standby Current
:
One bank; active / precharge;
CS
≥
V
IH (min)
;
CKE
≥
V
IH (min)
; t
RC
= t
RAS (max)
; DQ, DM, and DQS
inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
Operating Current:
One bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per
clock cycle; DQ and DQS outputs changing twice
per clock cycle; CL = 2.5; I
OUT
= 0mA
Operating Current
:
One bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per
clock cycle; DQ and DQS inputs changing twice
per clock cycle; CL = 2.5
Auto-Refresh Current
: t
RC
= t
RFC (min)
135
155
180
180
mA
1
I
DD1
165
185
210
210
mA
1
I
DD2P
3
3
3.5
3.5
mA
1
I
DD2N
60
60
65
65
mA
1
I
DD3P
50
55
65
65
mA
1
I
DD3N
105
120
140
140
mA
1
I
DD4R
230
255
300
300
mA
1
I
DD4W
215
250
290
290
mA
1
I
DD5
195
210
230
240
mA
1
I
DD6
Self-Refresh Current
: CKE
≤
0.2V
Operating curren
t:
Four bank; four bank interleaving with BL = 4,
address and control inputs randomly changing;
50% of data changing at every transfer; t
RC
= t
RC
(min)
; I
OUT
= 0mA.
3
3
3
4
mA
1.2
I
DD7
365
395
430
430
mA
1
Notes:
1. I
DD
specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
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