參數(shù)資料
型號(hào)： A48P3616
廠商： AMIC Technology Corporation
英文描述： CAP 270PF 50V CERAMIC MONO 5%
中文描述： 8米× 16位DDR內(nèi)存
文件頁數(shù)： 14/62頁
文件大?。?/td> 2214K
代理商： A48P3616
Preliminary
A48P3616
8M X 16 Bit DDR DRAM
Preliminary (September 2005, Version 0.0)
13
AMIC Technology, Corp.
Electrical Characteristics & AC Timing - Absolute Specifications (continued)
(0 °C
≤
TA
≤
70
°
C; VDD = VDDQ = 2.5V
±
0.2V (6K/75B); VDD = VDDQ = 2.6V
±
0.1V (5T/43), See AC Characteristics)
DDR266
75B
Symbol
Parameter
Min
Max
Address and control input hold time
(slow slew rate)
Address and control input setup time
(slow slew rate)
t
RPRE
Read preamble
0.9
1.1
t
RPST
Read postamble
0.40
0.60
t
RAS
Active to Precharge command
45
120,000
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-refresh
command period
t
RCD
Active to Read or write dalay
3
Active to read command with
Autoprecharge
t
RP
Precharge command period
3
Active bank A to Active bank B
command
t
WR
Write vecovery time
3
(t
WR/
t
CK
+
t
RP/
t
CK
)
t
WTR
Intemal write to read command delay
1
t
PDEX
Power down exit time
7.5
Exit self-refresh to non-read
command
t
XSRD
Exit self-refresh to read command
200
t
REFI
Average Periodic Refresh Interval
7.8
DDR333
6K
Min
DDR400
5T
Min
DDR466
43
Min
Max
Max
Max
Unit
Note
t
IH
1.0
0.8
0.7
0.7
ns
2-4,10,11,
12,14
t
IH
1.0
0.8
0.7
0.6
ns
2-4,10,11,
12,14
1-4
1-4
1-4
0.9
0.40
42
1.1
0.60
120,000
0.9
0.40
40
1.1
0.60
120,000
0.9
0.40
40
1.1
0.60
120,000 ns
t
CK
t
CK
t
RC
65
60
60
60
ns
1-4
t
RFC
12
12
13
15
t
CK
1-4
3
3
4
t
CK
1-4
t
RAP
3
3
3
4
t
CK
1-4
3
3
3
t
CK
1-4
t
RRD
2
2
2
3
t
CK
1-4
3
3
3
t
CK
1-4
t
DAL
Auto precharge write recovery +
precharge time
(t
WR/
t
CK
+
t
RP/
t
CK
)
1
6
(t
WR/
t
CK
+
t
RP/
t
CK
)
1
5
(t
WR/
t
CK
+
t
RP/
t
CK
)
2
5
t
CK
1-4,13
t
CK
ns
1-4
1-4
t
XSNR
13
13
10
10
t
CK
1-4
200
200
200
t
CK
μ
s
1-4
1-4,8
7.8
7.8
7.8
Notes:
1. Input slew rate = 1V/ns.
2. The CK/
CK
input reference level (for timing reference to CK/
CK
) is the point at which CK and
CK
cross; the input reference
level for signals other than CK/
CK
is V
REF
.
3. Inputs are not recognized as valid until V
REF
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT.
5. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously
in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be
HIGH, LOW, or transitioning from high to low at this time, depending on t
DQSS
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate
≥
1.0V/ns. Slew rate is measured between V
OH (AC)
and V
OL (AC)
.
10. For command/address input slew rate
≥
0.5V/ns and < 1.0V/ns. Slew rate is measured between V
OH (AC)
and V
OL (AC)
.
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