參數(shù)資料
型號(hào)： A48P3616
廠商： AMIC Technology Corporation
英文描述： CAP 270PF 50V CERAMIC MONO 5%
中文描述： 8米× 16位DDR內(nèi)存
文件頁(yè)數(shù)： 17/62頁(yè)
文件大小： 2214K
代理商： A48P3616
Preliminary
A48P3616
8M X 16 Bit DDR DRAM
Preliminary (September 2005, Version 0.0)
16
AMIC Technology, Corp.
Register Definition
Mode Register
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, and
an operating mode. The Mode Register is programmed via
the Mode Register Set command (with BA0 = 0 and BA1 = 0)
and retains the stored information until it is programmed
again or the device loses power (except for bit A8, which is
self-clearing).
Mode Register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved), A4-A6
specify the
CAS latency, and A7-A11 specify the operating mode. The
Mode Register must be loaded when all banks are idle, and
the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements
results in unspecified operation.
Burst Length
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations
that can be accessed for a given Read or Write command.
Burst lengths of 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a Read or Write command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst wraps within the block if a boundary is reached.
The block is uniquely selected by A1-Ai when the burst length
is set to two, by A2-Ai when the burst length is set to four and
by A3-Ai when the burst length is set to eight (where Ai is the
most significant column address bit for a given configuration).
The remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. The
programmed burst length applies to both Read and Write
bursts.
Mode Register Operation
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0*
0*
Operating Mode
CAS Latency
BT
Burst Length
Operating Mode
CAS Latency
Burst Type
Burst Length
A11-A9 A8 A7 A6-A0
Type
A6
A5
A4
Type
A3
Type
A2
A1
A0
Type
0
0
0
Valid
Normal operation
Do not reset DLL
Normal operation
in DLL Reset
Vendor-Specific
Test Mode
Reserved
0
0
0
Reserved
0
Sequential
0
0
0
Reserved
0
1
0
Valid
0
0
1
Reserved
1
Interleave
0
0
1
2
0
0
1
VS**
0
1
0
2
0
1
0
4
-
-
-
0
1
1
3 (Option)
0
1
1
8
1
0
0
Reserved
1
0
0
Reserved
1
0
1
1.5
(Option)
1
0
1
Reserved
1
1
0
2.5
1
1
0
Reserved
1
1
1
Reserved
1
1
1
Reserved
Note:
1. VS
**
Vendor Specif
ic
2.
*
BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
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