參數(shù)資料
型號: A48P3616
廠商: AMIC Technology Corporation
英文描述: CAP 270PF 50V CERAMIC MONO 5%
中文描述: 8米× 16位DDR內(nèi)存
文件頁數(shù): 23/62頁
文件大?。?/td> 2214K
代理商: A48P3616
Preliminary
A48P3616
8M X 16 Bit DDR DRAM
Preliminary (September 2005, Version 0.0)
22
AMIC Technology, Corp.
Precharge
The Precharge command is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s)
is available for a subsequent row access some specified time
(t
RP
) after the Precharge command is issued. Input A10
determines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any Read or Write commands
being issued to that bank.
Power Down
Power Down is entered when CKE is registered low (no
accesses can be in progress). If Power Down occurs when all
banks are idle, this mode is referred to as Precharge Power
Down; if Power Down occurs when there is a row active in
any bank, this mode is referred to as Active Power Down.
Entering Power Down deactivates the input and output
buffers, excluding CK, CK and CKE. The DLL is still running
in Power Down mode, so for maximum power savings, the
user has the option of disabling the DLL prior to entering
Power Down. In that case, the DLL must be enabled after
exiting Power Down, and 200 clock cycles must occur before
a Read command can be issued. In Power Down mode, CKE
Low and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, and all other input signals are
“Don’t Care”. However, Power Down duration is limited by the
refresh requirements of the device, so in most applications,
the self refresh mode is preferred over the DLL-disabled
Power Down mode.
The Power Down state is synchronously exited when CKE is
registered high (along with a Nop or Deselect command). A
valid, executable command may be applied one clock cycle
later.
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