參數(shù)資料
型號： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 20/172頁
文件大小： 1506K
代理商： PIC16CR7X
PIC16CR7X
DS21993C-page 18
2007 Microchip Technology Inc.
Bank 2
100h
(4)
101h
102h
(4)
103h
(4)
104h
(4)
105h
106h
107h
108h
109h
10Ah
(1,4)
PCLATH
10Bh
(4)
10Ch
10Dh
10Eh
10Fh
Bank 3
180h
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
27, 96
TMR0
Timer0 Module Register
xxxx xxxx
45, 96
PCL
Program Counter (PC) Least Significant Byte
0000 0000
26, 96
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
19, 96
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
27, 96
—
PORTB
—
—
—
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
—
—
xxxx xxxx
—
—
—
34, 96
—
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
26, 96
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21, 96
PMDATA
PMADR
PMDATH
PMADRH
Data Register Low Byte
Address Register Low Byte
—
—
xxxx xxxx
29, 97
29, 97
29, 97
xxxx xxxx
—
—
Data Register High Byte
—
xxxx xxxx
Address Register High Byte
xxxx xxxx
29, 97
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
27, 96
181h
182h
(4)
183h
(4)
184h
(4)
185h
186h
187h
188h
189h
18Ah
(1,4)
PCLATH
18Bh
(4)
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
20, 44, 96
PCL
Program Counter (PC) Least Significant Byte
0000 0000
26, 96
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
19, 96
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
27, 96
—
TRISB
—
—
—
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
—
—
1111 1111
—
—
—
34, 96
—
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
26, 96
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21, 96
18Ch
PMCON1
—
(6)
Unimplemented
Reserved maintain clear
Reserved maintain clear
—
—
—
—
—
—
RD
1--- ---0
29, 97
18Dh
18Eh
18Fh
Legend:
—
—
—
—
0000 0000
0000 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Details
on page
x
= unknown,
u
= unchanged,
q
= value depends on condition, – = unimplemented, read as ‘
0
’, r = reserved.
Shaded locations are unimplemented, read as ‘
0
’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (
CALL
or
GOTO
).
Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘
0
’.
This bit always reads as a ‘
1
’.
Note
1:
2:
3:
4:
5:
6:
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