參數(shù)資料
型號: 70T631S12DDGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 18 DUAL-PORT SRAM, 12 ns, PQFP144
封裝: 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144
文件頁數(shù): 8/27頁
文件大?。?/td> 220K
代理商: 70T631S12DDGI
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
16
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
NOTES:
1. DOR = DOL = VIL,
CE0L = CE0R = VIH; CE1L = CE1R = VIL. Refer also to Truth Table II for appropriate UB/LB controls.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/
W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTES:
1.
CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for
appropriate
UB/LB controls.
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17) equal to the semaphore value.
SEM(1)
5670 drw 12
tAW
tEW
I/O
VALID ADDRESS
tSAA
R/
W
tWR
tOH
tACE
VALID ADDRESS
DATA
VALID
IN
DATAOUT
tDW
tWP
tDH
tAS
tSWRD
Read Cycle
Write Cycle
A0-A2
OE
VALID(2)
tSOP
.
tSOE
SEM"A"
5670 drw 13
tSPS
MATCH
R/
W"A"
MATCH
A0"A"-A2"A"
SIDE
"A"
(2)
SEM"B"
R/
W"B"
A0"B"-A2"B"
SIDE
"B"
(2)
.
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