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參數(shù)資料
| 型號(hào)： | 70T631S12DDGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 DUAL-PORT SRAM, 12 ns, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144 |
| 文件頁數(shù)： | 18/27頁 |
| 文件大?。?/td> | 220K |
| 代理商： | 70T631S12DDGI |
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IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
5. JTAG cannot be tested in sleep mode.
JTAG Timing Specifications
TCK
Device Inputs(1)/
TDI/TMS
Device Outputs(2)/
TDO
TRST
tJCD
tJDC
tJRST
tJS
tJH
tJCYC
tJRSR
tJF
tJCL
tJR
tJCH
5670 drw 23
x
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4,5)
70T633/1
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
3(1)
ns
tJF
JTAG Clock Fall Time
____
3(1)
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
15
____
ns
tJH
JTAG Hold
15
____
ns
5670 tbl 20
Sleep Mode
The IDT70T633/1 is equipped with an optional sleep or low power
modeonbothports.Thesleepmodepinonbothportsisactivehigh.During
normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the
port will enter sleep mode where it will have the lowest possible power
consumption.Thesleepmodetimingdiagramdemonstratesthemodesof
operation: Normal Operation, No Read/Write Allowed and Sleep Mode.
Foraperiodoftime priortosleepmodeandafterrecoveringfromsleep
mode (tZZS and tZZR), new reads or writes are not allowed. If a write or read
operation occurs during these periods, the memory array may be
corrupted. Validity of data out from the RAM cannot be guaranteed
immediately after ZZ is asserted (prior to being in sleep).
DuringsleepmodetheRAMautomaticallydeselectsitselfanddiscon-
nectsitsinternalbuffer.Alloutputswillremaininhigh-Zstatewhileinsleep
mode.Allinputsareallowedtotoggle,buttheRAMwillnotbeselectedand
will not perform any reads or writes.
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| 70T631S15BC | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 2.5V 4M-Bit 256K x 18 15ns 256-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 2.5V 4.5MBIT 256KX18 15NS 256BGA - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:256K X 18 STD-PWR, 2.5V DUAL PORT RAM |
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