參數(shù)資料
型號： 70T631S12DDGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 256K X 18 DUAL-PORT SRAM, 12 ns, PQFP144
封裝： 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144
文件頁數(shù)： 13/27頁
文件大小： 220K
代理商： 70T631S12DDGI
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
20
Truth Table III — Interrupt Flag(1,4)
Waveform of Interrupt Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3.
CEX = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.
4. Timing depends on which enable signal (
CE or R/W) is asserted last.
5. Timing depends on which enable signal (
CE or R/W) is de-asserted first.
NOTES:
1. Assumes
BUSYL = BUSYR =VIH. CEX = L means CE0X = VIL and CE1X = VIH.
2. If
BUSYL = VIL, then no change.
3. If
BUSYR = VIL, then no change.
4.
INTL and INTR must be initialized at power-up.
5. A18x is a NC for IDT70T631. Therefore, Interrupt Addresses are 3FFFF and 3FFFE.
5670 drw 18
ADDR"A"
INTERRUPT SET ADDRESS
CE"A"(3)
R/
W"A"
tAS
tWC
tWR
(4)
(5)
tINS
(4)
INT"B"
(2)
.
5670 drw 19
ADDR"B"
INTERRUPT CLEAR ADDRESS
CE"B"(3)
OE"B"
tAS
tRC
(4)
tINR
(4)
INT"B"
(2)
.
Left Port
Right Port
Function
R/
WL
CEL
OEL
A18L-A0L(5)
INTL
R/
WR
CER
OER
A18R-A0R(5)
INTR
L
X
7FFFF
XXXX
X
L(2)
Set Right
INTR Flag
X
L
7FFFF
H(3)
Reset Right
INTR Flag
XXX
X
L(3)
L
X
7FFFE
X
Set Left
INTL Flag
X
L
7FFFE
H
(2)
X
Reset Left
INTL Flag
5670 tbl 17
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