參數(shù)資料
型號： 70T631S12DDGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 256K X 18 DUAL-PORT SRAM, 12 ns, PQFP144
封裝： 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144
文件頁數(shù)： 11/27頁
文件大小： 220K
代理商： 70T631S12DDGI
19
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1,3,4)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the
BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3.
CEX = VIL when CE0X = VIL and CE1X = VIH. CEX = VIH when CE0X = VIH and/or CE1X = VIL.
4.
CE0X = OEX = LBX = UBX = VIL. CE1X = VIH.
5670 drw 16
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"(3)
CE"B"(3)
BUSY"B"
tAPS
tBAC
tBDC
(2)
.
5670 drw 17
ADDR"A"
ADDRESS "N"
ADDR"B"
BUSY"B"
tAPS
tBAA
tBDA
(2)
MATCHING ADDRESS "N"
70T633/1S8(3)
Com'l Only
70T633/1S10
Com'l
& Ind
(3)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Symbol
Parameter
Min.Max.Min.Max.Min.Max.Min.Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
8
____
10
____
12
____
15
ns
tINR
Interrupt Reset Time
____
8
____
10
____
12
____
15
ns
5670 tbl 16
NOTES:
1. Timing is the same for both ports.
2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
3. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
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參數(shù)描述
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