參數(shù)資料
型號(hào)： 4565B2
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁(yè)數(shù)： 36/61頁(yè)
文件大?。?/td> 1691K
代理商： 4565B2
Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
41
5.4 TOAC, POAC, and LOPOH Timing
The relationships between data, clock, and sync signals are specific to the TOAC and POAC operation mode selected.
This is explained in detail in the TOAC/POAC chapter of the System Design Guide.
Note: For information pertaining to the output clock duty cycle (in various TOAC/POAC modes of operation), please refer to page 50 and page 51.
Figure 5-9. TOAC, POAC Timing
Note: For all modes, SYNC signals are high during the clock period of the first bit of each frame.
Figure 5-10. LOPOH Timing
Table 5-7. TOAC, POAC and LOPOH Inputs Specifications
Name
Reference
Edge
Rising/Falling
Max Rise
Time (ns)
Max Fall
Time (ns)
Min Setup
(ns)
Min Hold
(ns)
TTOACDATA
TTOACCLK (output)
R
10
3.5
0
TPOACDATA
TPOACCLK (output)
R
10
3.5
0
LOPOHDATAIN and
LOPOHVALIDIN
LOPOHCLKIN
F
8
5
Table 5-8. TOAC, POAC and LOPOH Outputs Specifications
Name
Reference
Edge Rising (R)
Falling (F)
Propagation Delay
Min (ns)
Max (ns)
RTOACDATA, RTOACSYNC
RTOACCLK
R
0
3.5
TTOACSYNC
TTOACCLK
R
0
3.5
RPOACDATA, RPOACSYNC
RPOACCLK
F
03.5
TPOACSYNC
TPOACCLK
R
0
3.5
LOPOHDATAOUT and LOPOHVALIDOUT
LOPOHCLKOUT
R
0
5
TPOACCLK
tPD
W68
W+
TTOACCLK
TPOACDATA
TTOACDATA
RPOACDATA
RTOACDATA
RPOACCLK
RTOACCLK
W68
W+
LOPOHCLKIN
LOPOHDATAIN
LOPOHDATAOUT
tPD
LOPOHCLKOUT
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