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參數(shù)資料
| 型號： | 4565B2 |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909 |
| 封裝： | PLASTIC, BGA-909 |
| 文件頁數(shù)： | 24/61頁 |
| 文件大?。?/td> | 1691K |
| 代理商： | 4565B2 |
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4565B Ultramapper Full Transport Retiming Device
Hardware Design Guide, Revision 2
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
December 17, 2003
30
Agere Systems Inc.
Table 2-23. General-Purpose Interface
Pin
Symbol
Type
Name/Description
AK18
RSTN
I pu
Global Hardware Reset. Active-low. Initializes all internal registers to their
default state. This is an asynchronous reset on the falling edge, but RSTN
should be held low for at least 1 s. RSTN should be held low until both
power supplies (1.5 V and 3.3 V) are stabilized upon powerup.
AJ24
PMRST
I/O pd Performance Monitor Reset. Resets error counters. When enabled as an
input, it is a 1s square wave that forces an update of PM counters upon the
rising edge. When the PMRST is generated internally from the MPU clock,
this pin is an output.
AL20
IC3STATEN
I pu
Output Enable. When high, output buffers will operate normally. When low,
all outputs will be forced to a high-impedance state. IC3STATEN should be
held low until both power supplies (1.5 V and 3.3 V) are stabilized upon pow-
erup
AP24
SCK1
I pd
Scan Clock 1. Reserved. Do not connect.
AM23
SCK2
I pd
Scan Clock 2. Reserved. Do not connect.
AJ23
SCAN_EN
I pd
Scan Enable. Reserved. Do not connect.
AK20
SCANMODE
I pd
Serial Scan Input for Testing. Reserved. Do not connect.
AL21
IDDQ
I
IDDQ Input. This pin must be externally pulled down with a 1 k
resistor.
Table 2-24. CDR Interface
Pin
Symbol
Type
Name/Description
AM13
BYPASS
I pd
High-Speed CDR Bypass. Reserved. Do not connect.
AG15
TSTPHASE
I pd
Test Phase. Reserved. Do not connect.
AL14
ECSEL
I pd
External Clock Select. Reserved. Do not connect.
AP15
ETOGGLE
I pd External Toggle. Reserved. Do not connect.
AP16
EXDNUP
I pd
External Down Up. Reserved. Do not connect.
AJ13
TSTMODE
I pd
Test Mode. Reserved. Do not connect.
AG7
TSTSFTLD
I pd
Test Shift Load. Reserved. Do not connect.
Table 2-25. Analog Power and Ground Signals
Pin
Symbol
Type
Name/Description
AP13
VSSA_CDR1
—
CDR1 Ground. Isolated ground for the internal CDR1.
AG13
VSSA_CDR2
—
CDR2 Ground. Isolated ground for the internal CDR2.
AK15
VSSA_X4PLL
—
X4PLL Ground. Isolated ground for the internal X4PLL.
AH31
VSSA_SFPLL
—
SFPLL Ground. Isolated ground for the internal SFPLL.
D18
VSSA_DS3PLL
—
DS3PLL Ground. Isolated ground for the internal DS3PLL.
A19
VSSA_E3PLL
—
E3PLL Ground. Isolated ground for the internal E3PLL.
AP14
VDD15A_CDR1
—
CDR1 Power. 1.5 V power supply for the internal CDR1, which is used by
the high-speed receive CDR, the protection receive CDR, and the three
CDRs associated with the mate interconnect ports. Good engineering prac-
tice needs to be applied; refer to the evaluation board schematic.
AL11
VDD15A_CDR2
—
CDR2 Power. 1.5 V power supply for the internal CDR2, which is used by
the high-speed receive CDR, the protection receive CDR, and the three
CDRs associated with the mate interconnect ports. Good engineering prac-
tice needs to be applied; refer to the evaluation board schematic.
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