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參數資料
| 型號： | 4565B2 |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909 |
| 封裝： | PLASTIC, BGA-909 |
| 文件頁數： | 33/61頁 |
| 文件大?。?/td> | 1691K |
| 代理商： | 4565B2 |
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Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
39
Figure 5-4. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 0)
When supplied externally, the 8 kHz THSSYNC may have a 50/50 duty cycle since the signal will only be sampled on the
rising edge. In this case, THSSYNC should be synchronous to THSC.
However, if the system needs to synchronize VTs, generated from different Ultramapper FT Retiming devices or other ex-
ternal devices, then THSSYNC needs to look like the waveform representation in Figure 5-5, i.e., THSSYNC must be com-
posed of both the 8 kHz and the 2 kHz sync components (J0 + V1-1—V1-3); the J1 portion is not needed.
Figure 5-5. THSSYNC Timing Diagram for Synchronized VTs
The Figure 5-6 depicts the relationship between the rising edge of the input THSSYNC (when the device is in slave mode)
and the beginning of the SONET frame output on THSD. The delay between THSSYNC and the start of the outgoing SONET
frame is contributed to internal device delays (pertaining to multiplexing functionality, FIFO, and parallel to serial conversion).
Figure 5-6. Relationship Between THSSYNC and THSD
STS-3
J0
FIRST FRAME
50 ns
STS-12
50 ns
125
s
125
s
J0
SECOND FRAME
THIRD FRAME
FOURTH FRAME
SECOND FRAME
THIRD FRAME
FOURTH FRAME
FIRST FRAME
J0
STS-3
J0
V1-1
FIRST FRAME
50 ns
SECOND FRAME
THIRD FRAME
FOURTH FRAME
STS-12
V1-2
V1-3
J0
V1-1
V1-2
V1-3
50 ns
J0
FIRST FRAME
SECOND FRAME
THIRD FRAME
FOURTH FRAME
THSSYNC
THSD
A1
N
622 Mbits/s mode: N = 80 +/- 8 bits
155 Mbits/s mode: N = 44 +/- 8 bits
For the case where TMUX_TLBITCNT, TMUX_TLSTSCNT, TMUX_TLCOLCNT, and TMUX_TLROWCNT all = 0 (default).
Changing these register values will change the location of point X in relation to point Y
X
Y
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