參數(shù)資料
型號(hào)： 4565B2
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁(yè)數(shù)： 30/61頁(yè)
文件大?。?/td> 1691K
代理商： 4565B2
4565B Ultramapper Full Transport Retiming Device
Hardware Design Guide, Revision 2
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
December 17, 2003
36
Agere Systems Inc.
* The following bidirectional pins can sink/source 10 mA: NSMIRXCLK[3:1].
4.4.2 LVDS Interface Characteristics
3.3 V ± 5% VDD, –40 °C to +125 °C junction temperature.
.
Table 4-6. LVCMOS Bidirectionals Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Leakage Current
IL
VSS < VIN < VDD33
——
11
A
High-input Voltage
VIH
—2.0
—
VDD33 + 0.3
V
Low-input Voltage
VIL
—VSS
—0.8
V
Biput Capacitance
CIB
—
5.0
—
pF
Output Voltage Low
VOL
IOL = –6 mA*
—
0.5
V
Output Voltage High
VOH
IOH = 6 mA*
2.4
—
V
Table 4-7. LVDS Interface dc Characteristics
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Buffer Parameters
Input Voltage Range
High (V,$ or V,%)
Low (V,$ or V,%)
VI
VIH
VIL
|VGPD| < 925 mV, dc—1 MHz
—
0
—
2.4
—
V
Input Differential Threshold
VIDTH
dc— 450 MHz
–100
—
100
mV
Input Differential Hysteresis
VHYST
(+VIDTH) – (–VIDTH)—
—
—*
mV
Receiver Differential Input
Impedance
RIN
With build-in termination, center-tapped
80
100
120
Output Buffer Parameters
Output Voltage:
High (V2$ or V2%)
Low (V2$ or V2%)
VOH
VOL
RLOAD = 100
± 1%
RLOAD = 100
± 1%
—
0.925
—
1.475
—
V
Output Differential Voltage
|VOD|RLOAD = 100
± 1%
0.25
—
0.45
V
Output Offset Voltage
VOS
RLOAD = 100
± 1%
1.125
—
1.275
V
Output Impedance, Single Ended
RO
VCM = 1.0 V and 1.4 V
80
100
120
RO Mismatch Between A and B
RO
VCM = 1.0 V and 1.4 V
—
10
%
Change in Differential Voltage
Between Complementary States
|
VOD|RLOAD = 100 ± 1%
—
25
mV
Change in Output Offset Voltage
Between Complementary States
VOS
RLOAD = 100
± 1%
—
25
mV
Output Current
ISA, ISB
Driver shorted to VSS
——
24
mA
Output Current
ISAB
Drivers shorted together
—
12
mA
* The buffer will not produce output transitions when input is open-circuited. When the true and complement inputs are floating, the input buffer will not
oscillate.
250 mV
≤ |VA – VB| ≤ 450 mV
Note: The characteristics in the table above apply under the following conditions:
External LVDS reference chosen (UMPR_LVDS_REF_SEL = 0).
REF10 = 1.0 V ±3% and REF14 = 1.4 V ±3%.
Internal LVDS reference chosen (UMPR_LVDS_REF_SEL = 1).
VDD33 supply controlled to within ± 3%.
When UMPR_LVDS_REF_SEL = 1, the internal reference levels are derived using a resistor ladder from VDD33. These levels will vary as much as the
VDD33 supply does and are therefore only as accurate as the VDD33. If VDD33 cannot be controlled to within ± 3%, one or more IEEE specifications
may be violated. While this may not necessarily lead to data errors during transmission, interoperability issues may arise due to specification noncompli-
ance.
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