參數(shù)資料
型號： 4565B2
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁數(shù)： 32/61頁
文件大小： 1691K
代理商： 4565B2
4565B Ultramapper Full Transport Retiming Device
Hardware Design Guide, Revision 2
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
December 17, 2003
38
Agere Systems Inc.
5.2 THSSYNC Characteristics
THSSYNC is an 8 kHz composite frame sync pulse for STS-3 or STS-12. THSSYNC contains J0, J1, and V1-1 information
as shown in Figure 5-3. The time delay from any rising edge of a J0 (8 kHz) to the rising edge of the next J0 is 125 s. The
time delay between any two V1-1 (2 kHz) pulses is 500 s. This is true whether in STS-3 or STS-12 mode.
When MPU_MASTER_SLAVE = 1, then THSSYNC is according to Figure 5-3.
Figure 5-3. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 1)
When MPU_MASTER_SLAVE = 0, then THSSYNC (supplied from an external source) can be according to Figure 5-4.
Table 5-2. Protection Link Inputs Specifications
Name
Reference
Edge
Rising/Falling
Max Rise
Time (ns)
Max Fall
Time (ns)
Min Setup
(ns)
Min Hold
(ns)
RPSDP/N (622 MHz)*
* Input serial data stream should have minimum eye opening of 0.4 UIp-p, and no more than 60 consecutive bits that have no transitional edge
within one minute. It must meet 100 ps maximum phase variation limit over a 200 ns interval; this translates to a frequency change of 500 ppm.
Asynchronous
—
0.5
—
RPSDP/N (155 MHz)