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| 型號： | 4565B2 |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909 |
| 封裝： | PLASTIC, BGA-909 |
| 文件頁數(shù)： | 1/61頁 |
| 文件大小： | 1691K |
| 代理商： | 4565B2 |
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Hardware Design Guide, Revision 2
December 17, 2003
4565B Ultramapper Full Transport Retiming Device
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
1 Introduction
A change history is included in Section 12, Change History, on page 60.
The documentation package for the 4565B Ultramapper Full Transport Retiming Device 622/155 Mbits/s SONET/SDH x
DS3/E3/DS2/DS1/E1 system chip consists of the following documents:
I The Register Description and the System Design Guide. These documents are available on a password-protected web-
site.
I The 4565B Ultramapper Full Transport Retiming Device Product Description and the 4565B Ultramapper Full Transport
Retiming Device Hardware Design Guide (this document). These documents are available on the public website shown
below (select Mappers/MUXes):
http://www.agere.com/enterprise_metro_access/index.html
This document describes the hardware interfaces to the Agere Systems 4565B Ultramapper Full Transport Retiming
Device. Information relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical
characteristics, timing diagrams, ac timing parameters, packaging, and operating conditions are included.
If the reader saves this document to disk and displays it using Acrobat Reader , clicking on any blue text will bring the
reader to that reference point. Clicking on the back arrow (Go to previous View) in the toolbar of the Acrobat Reader will
bring the reader back to the starting point.
To contact Agere Systems, see the last page of this document or contact your Agere representative.
Figure 1-1. 4565B Ultramapper Full Transport Retiming Device Block Diagram and High-Level Interface Definition
(x3)
M13
MUX
TMUX
STS-12/
STM-4/
STS-3/
STM-1
FRM (X3)
x28/x21
DS1/J1/E1
(x3)
x28/x21
VTMPR
MRXC
DS1/J1/E1
VT/TU
DS2/E2
DS3/E3
TPG/TPM
X3
x28/x21
DS1/E1
DJA
CDR
SPEMPR
(x3)
(0-2)
CDR
MCDR
STSPP
MPU
JTAG
LOPOH
x6
DS3/E3
DJA
(x3)
E13
MUX
SPEMPR
(x3)
(3-5)
(x3)
STS-1
LT
3
1
S
T
S
X
C
System Interfaces
Transport Modes
4
4DS1/J1/E1 (x86): x84/x63 + prot.
4
4DS2/E2 (X86): x63/x36 + prot.
(x6) DS3/E3
(x3) STS-1
(x3) NSMI
(x3) STS-1
(Total of 3 STS-1 Max)
Low-Speed I/O
622 Mb/STS-12/STM-4
155 Mb/STS-3/STM-1
Clock and Data
LOPOH
622/155 Mbits/s SONET/SDH
ADM Front End
DS3/E3/DS2/DS1/E1 PDH
Tributary Termination
TOAC
MPU IF
POAC
JTAG IF
66
E2,
VC12
DS3XCLK,
E3XCLK
DS2,
VC11
AIS Clocks
DS1XCLK,
E1XCLK
Power and GND pins not shown
12
49
5
6
STS-3/STM-1 Mate
Interconnect
High-Speed IF
(x3)
8
Clock/Sync
6
Protection Link
622 Mb/STS-12/STM-4
155 Mb/STS-3/STM-1
Clock and Data
8
42
24
344
3
1
2
10/10/02
Miscellaneous
24
CG
FRM PLL IF
5
Retiming
Rx/Tx Clocks and
Syncs
5
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