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Chapter 1 Architectural Overview
Indirect Pointers
Special registers
sr128–sr130
, better known as IPA, IPB and IPC, are the indi-
rect pointers used to access the general purpose register file. For instructions which
make use of the three operand fields, RA, RB and RC, to address general purpose
registers, the indirect pointer can be used as an alternative operand address source.
For example, the RA operand field supplies the register number for the source oper-
and–A; if global register address
gr0
is used in the RA instruction field, then the oper-
and register number is provided by the IPA register.
The IPA, IPB and IPC registers are pointers into the global register file. They are
generally used to point to parameters passed to User mode helper routines. They are
also used to support instruction emulation, where trap handler routines perform in
software the
missing
instruction. The operands for the emulated instruction are
passed to the trap handler via the indirect pointers.
ALU Support
Special registers
sr131–sr134
support arithmetic unit operation. Register
sr131
, better known as Q, is used during floating–point and integer multiply and di-
vide steps. Only the Am29050 processor can perform floating–point operations di-
rectly, that is, without coprocessor or software emulation help. It is also the only pro-
cessor which directly supports integer multiply. All other current members of the
29K family perform these operations in a sequence of steps which make use of the Q
register.
The result of a comparison instruction is placed in a general purpose register, as
well as in the condition field of the ALU status register (special register
sr132
). How-
ever, the ALU status register is not conveniently tested by such instructions as condi-
tional branch. Branch decisions are made on the basis of True or False values held in
general purpose registers. This makes a lot of sense, as contention for use of a single
resource such as the ALU status register would lead to a resource conflict which
would likely result in unwanted pipeline stalling.
The ALU status register controls and reports the operation of the processor inte-
ger operation unit. It is divided into a number of specialized fields which, in some
cases, can be more conveniently accessed via special registers
sr134
and
sr135
. The
short hand
access provided by these additional registers avoids the read, shift and
mask operations normally required before writing to bit–fields in the ALU register.
Data Access Channel
The three channel control registers, CHA, CHD and CHC, were previously de-
scribed in the protected special registers section. However, User mode programs
have a need to establish load– and store–multiple operations which are controlled by
the channel support registers. Special register
sr135
, known as CR, provides a means
for a User mode program to set the Count Remaining field of the protected CHC reg-
ister. This field specifies the number of consecutive words transferred by the multiple