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October 13 1995, Draft 1
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Addendum to –– Evaluating and Programming the 29K RISC Family
With the Am29040 processor, the address bus A31–A0 of the slave (the tracing
processor) along with output pins REQ, R/W and I/D report physical branch address-
es even if the target instruction is provided by the on–chip instruction cache. By trac-
ing the slave processor signals along with the master, it is possible to exactly recon-
struct the sequence of instructions executed. Instruction execution is considered con-
secutive until a further nonsequential event (such as a branch or an interrupt) is re-
ported by the slave processor.
When a load or store hits in the data cache, the Am29040 slave processor pro-
vides the corresponding physical address on its address bus. The slave also indicates
when a data access results in cache block allocation. When an instruction executes,
the corresponding processor status (signals STAT2–STAT0) are reported on the fol-
lowing cycle –– when the instruction is in the write–back pipeline stage. Load and
store instructions are reported in the same way as other instructions, at the write–back
stage, rather than when the actual data transfer is accomplished.
The Am29040 and Am29030 processors perform traceable caching at the inter-
nal speed of the processor, this may be twice the speed of the off–chip memory sys-
tem. This ensures that the processor operation can always be fully reported. The
Am29240 microcontroller performs traceable caching at the off–chip memory sys-
tem speed. This can lead to difficulties when the processor is running internally at
twice the memory system speed. For example, it is not possible to report the target
address of the first jump in a back–to–back sequence of jump instructions (instruc-
tion visiting). Only the target of the second jump is reported by the Am29240 slave
processor. Additionally, if a branch instruction executes in the same memory cycle as
a load or store instruction, the slave only reports the address of the branch instruction.
Traceable caching is enabled via the JTAG interface. A boundary–scan instruc-
tions for enabling or disabling tracing can be entered via the JTAG port. Corelis Inc.
manufacture preprocessor boards supporting traceable caching. The preprocessor
contains two processors: a master and a slave. The second processor is switched into
slave–type operation during reset Active components on the preprocessor board
drive a TRACECACHE instruction into the slave processor. Around the perimeter of
the Am29040 preprocessor are nine logic analyzer connectors. An unusually large
number of analyzer pods is required due to the need to trace both master and slave
operation. In the Am29040 case, it is possible to operate with a minimum of eight
pods if the optional connector J7 is eliminated. This enables tracing to be accom-
plished with a minimum of two HP16550A or two HP16555A logic analyzer cards
inserted into an HP16500B analyzer system.
The analyzer cards cards should be connected together in master and slave
mode. This requires physically connecting ribbon cables on the cards. The cards can
be placed anywhere in the HP16500B card cage, as MonTIP scans for their actual
location. Assuming two HP16550A cards are located in slots D and E, pod E1 (slot E)
should be connected to position J1 on the Corelis preprocessor, and pod E2 to J2, and