
423
Chapter 8 Selecting a Processor
ramwrite
rampage
rampread
rampwrite
ramwidth
3
true
2
2
32
;pagemode on
;32–bit DRAM space
By building new event files, it is possible to re–run simulations and evaluate the
effect on the system’s performance. The simulator was run using the command
below:
sim29 –29200 –e 200_3232_2232.evt a.out
The program being simulated, shown as a.out above, was the LAPD
benchmark. I chose to use LAPD rather than Stanford because of the high instruction
cache hit ratio of the Stanford benchmark –– above 90% with even very small caches.
I believe modeling the performance of LAPD is more likely to reflect the actual
performance most users will experience with their own application code. However,
as always, I urge you to use your own code when benchmarking various processors.
The LAPD benchmark is good at testing data movement and bit field (packet header)
operations, but this may not be your requirement. Additionally, the Metaware
compiler was used with a high level of optimization (–07) when compiling the
benchmark. This produces the best performance but may require additional memory
to hold the expanded code which results from such optimizations as loop unrolling.
8.1.1 Selecting a Microcontroller
Microcontrollers are studied and grouped in this section according to their
memory system speed. Initially, systems based on 16 MHz memory are analyzed.
The performance of both 16– and 32–bit wide memories is presented. However, no
8–bit systems are included. Very small systems based on 8–bit memories and using
the Am2920x microcontrollers are evaluated in a separate section (section 8.1.2,
Moving up to an Am2920x Microcontroller
). Memory systems operating at 12.5
MHz are also dealt with in the section dealing with very small systems.
16 MHz Memory Systems
Setting 12.5 MHz systems aside, 16 MHz is the entry level system speed. This
can be achieved using a 16 MHz Am29200, Am29205 or Am29245 processor, or an
Am29240 using Scalable Clocking. When Scalable Clocking technology is used, a
33 MHz Processor would be combined with a 16 MHz memory system. Both
instruction and data accesses are satisfied by the slower 16 MHz memory. The
simulation results for various systems running the LAPD benchmark are shown in
Figure 8-1. Memory access times for the evaluated systems are shown in the
notation: (initial/subsequent), for example 2/1.
Programmable Data width was used to model 16–bit and 32–bit memories. As
expected and supported by the results, the 16–bit memory systems offer less