
xv
Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 1-5.
Figure 1-6.
Figure 1-7.
Figure 1-8.
Figure 1-9.
Figure 1-10.
Figure 1-11.
Figure 1-12.
Figure 1-13.
Figure 1-14.
Figure 1-15.
Figure 1-16.
Figure 1-17.
Figure 1-18.
Figure 1-19.
Figure 1-20.
Figure 1-21.
Figure 1-22. Instruction Format
Figure 1-23. Frequently Occurring Instruction–Field Uses
Figure 1-24.
Pipeline Stages for BTC Miss
RISC Pipeline
CISC Pipeline
Processor Price–Performance Summary
Am29000 Processor 3–bus Harvard Memory System
The Instruction Window for Out–of–Order Instruction Issue
A Function Unit with Reservation Stations
Register Dependency Resolved by Register Renaming
Circular Reorder Buffer Format
Multiple Function Units with a Reorder Buffer
Instruction Decode with No Branch Prediction
Four–Instruction Decoder with Branch Prediction
Am29200 Microcontroller Address Space Regions
Am29200 Microcontroller Block Diagram
General Purpose Register Space
Special Purpose Register Space for the Am29000 Microprocessor
Am29000 Processor Program Counter
Additional Special Purpose Registers for the Monitor Mode Support
Additional Special Purpose Registers for the Am29050 Microprocessor
Additional Special Purpose Registers for Breakpoint Control
Additional Special Purpose Registers for On–Chip Cache Control
Additional Special Purpose Register for the Am29050 Microprocessor
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