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Evaluating and Programming the 29K RISC Family
consideration use interrupt tagwords to support interrupt context caching for
Freeze mode handlers
An interrupt can be configured to generate a task context switch, the new task
being responsible for completing interrupt processing. This method has a
greater overhead associated with it than processing the interrupt in the context
of the interrupted task. Task context switching requires the register cache to be
flushed and reloaded with the incoming task’s register data. A C–level interrupt
handler can use the stack cut–across technique to avoid flushing the register
cache. Certainly some interrupts must cause task context switching to occur, but
it is best to avoid this approach as a general mechanism for dealing with
interrupts. Additionally, if tasks run in User mode, the instruction cache must be
flushed on a task context switch. It is best to reduce the number of cache flushes
due to interrupt support.
If the system is to support a high interrupt throughput, then processing interrupts
with a Dispatcher will be more efficient. The Dispatcher can execute in
assembly level or C level. If C, then the interrupted register stack condition need
only be repaired once before entering the Dispatcher, rather than for every
interrupt (see section 2.5.6).
Interrupt latency can be reduced if Freeze mode interrupt processing is never
disabled. For a HIF conforming operating system, the technique was described
in section 2.5.7 (
Minimizing Interrupt Latency
).
Synchronous context switching times are greatly improved by only restoring
the activation record of the procedure about to start execution. This can only be
done for tasks which were synchronously switched out; but is a better method
than restoring the register stack to the exact position in use at the time of the task
context save.
Many embedded operating systems run tasks in Supervisor mode rather than
User mode. This gives each task direct access to critical resources, there is no
need to use system calls (which use a trap instruction to enter Supervisor mode)
to gain access to restricted resources. Always running in Supervisor mode has
the additional advantage that the Instruction cache need not be flushed on a task
context switch. However, the benefits of memory access protection are typically
reduced or unavailable with such systems.
Operating systems each have their own system call interface which is usually a
little different from HIF (see Appendix C). However, it may be still useful to
have HIF services available. The HIF services can often be supported by
translating them into the underlying operating system serves. The High C 29K
and GNU library services generate HIF service calls. These libraries can be used
with a non–HIF operating system; but care must be taken as library routines