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Evaluating and Programming the 29K RISC Family
Integer operations complete in a single cycle, enabling the result of the previous
integer operation to be written back to the general purpose register file in the current
cycle. Because external memory reads are likely to take several cycles to complete,
and pipeline stalling is to be avoided, the accessed data value is not written back to the
global register file during the following instruction (the write–back cycle). This re-
sults in the load data being held by the processor until access to the write–back port is
available. This is certain to occur during the execution of any future load or store
instruction which itself can not make use of its
own
write–back cycle. The processor
makes available via
load
forwarding
circuitry the load data which awaits write–back
to the register file.
Register Access Protection
Special register
sr7
, known as RBP (register bank protect), provides a means to
restrict the access of general purpose registers by programs executing in User mode.
General purpose registers starting with
gr64
are divided into groups of 16 registers.
When the corresponding bit in the RBP register is set, the associated bank of 16 regis-
ters is protected from User mode access. The RBP register is typically used to prevent
User mode programs from accessing Supervisor–maintained information held in
global registers
gr64–gr95
. These registers are reserved by the AMD high level lan-
guage calling convention for system level information.
On–Chip Timer Control
Special registers
sr8
and
sr9
, known as TMC (timer counter) and TMR (timer
reload value), support a 24–bit real–time clock. The TMC register decrements at the
rate of the processor clock. When it reaches zero it will generate an interrupt if en-
abled. In conjunction with support software these two registers can be used to imple-
ment many of the functions often supported by off–chip timer circuitry.
Program Counter
A 29K processor contains a Master and Slave PC (program counter) address
register. The Master PC register contains the address of the instruction currently be-
ing fetched. The Slave contains the next sequentional instruction. Once an instruc-
tion flows into the execution unit, unless interrupted, the following instruction, cur-
rently in decode, will always flow into the execution unit. This is true for all instruc-
tions except for instructions such as IRET. Even if the instruction in execute is a
jump–type, the following instruction known as the delay–slot instruction is executed
before the jump is taken. This is known as delayed branching and can be very useful
in hiding memory access latencies, as the processor pipeline can be kept busy execut-
ing the delay–slot instruction while the new instruction sequence is fetched. It is an
important activity of high level language compilers to find useful instructions to
place in delay–slot locations.
The Master PC value flows along the PC–bus and the bus activity is recorded by
the PC buffer registers, see Figure 1-16. There are three buffer registers arranged in