
234
Evaluating and Programming the 29K RISC Family
from the value in
rfb
to determine the aligned
rab
value. This was done before issuing
an IRET to
sigcode
.
Essentially, this restores
rab
to where it pointed immediately before executing
the function call that caused the
FILL
operation. Note that this recomputation is also
valid for a normal case, where the management registers are consistent.
The two comparisons shown below determine which method, if any, should be
used to repair the value in register
gr1
. The method depends on whether a
longjmp
,
SPILL
, or normal interrupt occurred. This is required to align
gr1
to a valid cache
position where
longjmp
or
SPILL
is interrupted. The following code fragment
shows the code associated with the
lower
and
raise
labels.
;lower or raise value in gr1
lower:
jmp
add
sendsig
gr1,rfb,0
;set gr1 = rfb
raise:
jmp
add
sendsig
gr1,rab,0
;set gr1 = rab
According to the situation depicted in Figure 4-10, when a
SPILL
operation is
interrupted, code at the
raise
label is executed; however, the code resumes at the label
sendsig
.
The code fragment titled “fix–up registers to restart FILL operation”, shown
above, is entered if the interrupt occurred during a
FILL
operation. If so, it is neces-
sary to change the saved values for the Program Counters,
PC0 and PC1, and clear the
value saved in the CHC register. These registers are assumed to have been saved in
the order shown in Figure 4-8. This is required in addition to realigning the register
stack support register,
rab
.
The identifiers called SIGCTX_RAB, and SIGCTX_SIG are defined as numer-
ic offsets (to be added) to the memory stack address held in register
msp
. Making
these changes will effectively restart the
FILL
operation from its beginning. This
code also falls into the code beginning at label
nfill
, but in the case of an interrupted
FILL
operation, the value in register
gr1
will not be adjusted.
4.4.7 Preparing the C Environment
After stack repairs have been made to the (possibly inconsistent) management
registers, it is necessary to prepare for C language interrupt handler code execution.
These preparations consist mainly of setting up a new stack frame from which the
user’s handler can execute. At this point in the process, the register stack and memory
cache appear as shown in Figure 4-11.
The following code fragment picks up at the label
sendsig
, which is repeated for
clarity. The handler is almost ready to pass control to the user’s C language handler
code, but first it must set up a stack frame that looks as though the user’s function was