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Chapter 1 Architectural Overview
via
gr96
, a data value produced by the first instruction. The register label
gr96
is
merely used as an identifier for the data flow. What is intended is that data be passed
from the first instruction to the second. If our intentions could be communicated
without restricting data passing to
gr96
, then the third instruction could be executed
before the second.
The problem can be overcome by using register renaming, see section 1.7.3.
Briefly, when the first instruction in the above example is issued, it writes its result to
a temporary register identified by the name
gr96
. The second instruction receives its
operand from the same temporary register used by the first instruction. Execution of
the third instruction need not be stalled if it writes its result to a different copy of
register
gr96
. So now there are multiple copies of
gr96
. What really happens is
temporary registers are
renamed
to be
gr96
for the duration of the data flow. These
temporary registers play the role of registers indicated by the instruction sequence.
They are tagged to indicate the register they are duplicating.
1.7.2 Reservation Stations
Each function unit has a number of reservation stations which hold instructions
and operands waiting for execution, see Figure 1-6. All the reservation stations for
each function unit combined represent the instruction window from which
instructions are issued. The decoder places instructions into reservation stations
[Tomasulo 1967] with copies of operands, when available. Otherwise operand values
are replaced with tags indicating the register supplying the missing data. Placing a
copy of a source operand into the reservation station when an instruction is decoded,
prevents the operand being updated by a future instruction; and hence eliminates
anidependency conflicts. A function unit issues instructions to its execute stage when
it is not busy and a reservation station has an instruction ready for execution. Once an
instruction is placed in a reservation station, its issue occurs regardless of any
instruction issue occurring in another function unit. There can be any number of
reservation stations attached to a function unit. The greater the number, the larger the
instruction window; and the further ahead the processor can decode and issue
instructions. Additionally, a greater number of reservation stations prevents short
term demands on a function unit resulting in decoder–stalling.
An instruction may be stalled in a reservation station when a data dependency
causes a tag, rather than data, to be placed in the operand field. The necessary data
will become available when some other instruction completes and the result made
available. The instruction producing the required data value may be in a reservation
station or in execution in the same function unit, or in another function unit. Result
values are tagged indicating the register they should be placed in. With a scalar
processor, the result is always written to the instruction’s destination register. But
when register renaming is used by a superscalar processor, results are written to a
register which is temporarily playing the role of the destination register. These