
98
Evaluating and Programming the 29K RISC Family
ter spill operation is necessary to accommodate the local register requirements of the
called function. Register
rab
is normally initialized to be a window distance (512 by-
tes) below the
rfb
register value
Memory Stack Pointer (gr125)
The memory stack pointer (
msp
) register points to the top of the memory stack,
which is the lowest-addressed entry on the memory stack. Register
msp
should be
initialized to point to the highest address in the memory region allocated for memory
stack use. It is recommended that this region not be less than 2k bytes.
Am29027 Floating–Point Coprocessor Support
The Am29027 floating–point coprocessor has a
mode
register which has a
cumbersome access procedure. To avoid accessing the
mode
register a shadow copy
is kept by the operating system and accessed in preference when a
mode
register read
is required. The operating system shadow mode value is not accessible to User mode
code, therefore an application must maintain its own shadow
mode
register value.
The floating–point library code which maintains and accesses the shadow mode val-
ue, is passed the
mode
setting, initialized by the operating system, when
crt0
code
commences. Before entering
crt0
, the Am29027
mode
register value is copied into
global registers
gr96
and
gr97
. Register
gr96
contains the most significant half of the
mode
register value, and
gr97
contains the least significant half.
Open File Descriptors
File descriptor 0 (corresponding to the standard input device) must be opened
for text mode input. File descriptors 1 and 2 (corresponding to standard output and
standard error devices) must be opened for text mode output prior to entry to the
user’s program. File descriptors 0, 1, and 2 are expected to be in COOKED mode (see
Appendix A,
ioctl()
service), and file descriptor 0 should also select ECHO mode, so
that input from the standard input device (
stdin
) is echoed to the standard output de-
vice (
stdout
).
Software Emulation and Trapware Support
A 29K processor may take a trap in support of the procedure call prologue and
epilogue mechanism. A HIF conforming operating system supports the associated
SPILL and FILL traps by normally maintaining two global registers (in the
gr64
–
gr95
range) which contain the address of the users spill and fill code. Keeping
these addresses available in registers reduces the delay in reaching the typically User
mode support code. A HIF conforming operating system also installs the SPILL and
FILL trap handler code which
bounces
execution to the maintained handler address-
es.