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參數(shù)資料
| 型號： | 28F640W30 |
| 廠商： | Intel Corp. |
| 元件分類： | DRAM |
| 英文描述： | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 中文描述： | 1.8伏英特爾無線閃存的3伏的I / O和SRAM（寬30） |
| 文件頁數(shù)： | 19/82頁 |
| 文件大?。?/td> | 749K |
| 代理商： | 28F640W30 |
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28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
13
Burst mode is
not
the default mode after power-up or a device reset. To perform a burst-mode read,
the configuration register must be set. To set the configuration register, refer to
Section 4.2,
“
Set
Configuration Register (CR)
”
on page 13
. After setting the configuration register, if the first device
operation is a burst-mode read, it is not necessary to execute the Read Array command before
accessing the flash memory. However, to perform a flash read at any other time, it is necessary to
execute the Read Array command before accessing the flash memory array.
Burst mode is permitted in all blocks, across all partition boundaries and operates independently of
V
PP.
A single-word burst-mode read
cannot
be used to access register information. In burst mode,
the address is latched by either the rising edge of ADV# or the rising edge of CLK with ADV# low,
whichever occurs first.
Upon completion of reading the array, the device automatically enters an Automatic Power Savings
(APS) mode. APS mode consumes power comparable to standby mode.
4.2
Set Configuration Register (CR)
The configuration register is 16 bits wide. This register is used to configure the burst mode
parameters. Therefore, if using page mode, it is not necessary to set this register.
To set the configuration register, execute the Set Configuration Register command. The 16 bits of
data used by this command must be placed on address lines A
15
–
0
. All other address lines must be
held low (V
IL
).
After setting the configuration register, if the first device operation is a flash burst-mode read, it is
not necessary to execute the Read Array command before accessing the flash memory. However, to
perform a burst-mode read at any other time, it is necessary to execute the Read Array command
before accessing the flash memory.
NOTES:
1.
‘
R
’
bits are reserved bits. These bits and all other address lines must be set low.
2. On power-up or return from reset, all bits are set to
“
1.
”
Table 6. Configuration Register Bits
Configuration Register Bits
2
A
15
A
14
R
1
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
R
1
A
4
R
1
A
3
A
2
A
1
A
0
RM
LC
2-0
WT
DOC
WC
BS
CC
BW
BL
2-0
0
0
0
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