參數(shù)資料
型號： 28F640W30
廠商： Intel Corp.
元件分類： DRAM
英文描述： 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
中文描述： 1.8伏英特爾無線閃存的3伏的I / O和SRAM（寬30）
文件頁數(shù)： 18/82頁
文件大?。?/td> 749K
代理商： 28F640W30
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
12
Preliminary
Wireless Flash Memory Flash Memory family
’
s LPA is at 0080h.
PA = User programmable 4-word protection address in the device identification plane.
PnA = Address within the partition.
XnA = Base Address where X can be partition, main block or parameter block. See
Figure 11,
“
Device
Identification Codes
”
on page 21
for details.
QA = Query code address.
WA = Word address of memory location to be written.
2. SRD = Data read from the status register on DQ
7-0.
WD = Data to be written at location WA.
IC = Identifier code data.
PD =User programmable 4-word protection data.
QD = Query code data on DQ
.
CD = Configuration register code data presented on device addresses A
. A
address bits can select
any partition
.
See
Table 6,
“
Configuration Register Bits
”
on page 13
for configuration register bits
descriptions.
3. Commands other than those shown above are reserved by Intel for future device implementations and
should not be used.
.
4.0
Flash Read Modes
4.1
Read Array
4.1.1
Asynchronous Mode
The 1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O supports asynchronous reads. An
asynchronous read is executed by implementing a read operation without the use of the CLK
signal. During an asynchronous read operation, the CLK signal is ignored. If asynchronous reads
will be the only read mode of operation, it is recommended that the CLK signal be held at a valid
V
IH
level.
Page mode is the default read mode after power-up or reset. A page-mode read outputs 4 words of
asynchronous data; however, by manipulating certain control signals, the device can be made to
output less than 4 words.
After power-up or reset, it is not necessary to execute the Read Array command before accessing
the flash memory. However, to perform a flash read at any other time, it is necessary to execute the
Read Array command before accessing the flash memory.
Page mode is permitted in all blocks, across all partition boundaries and operates independent of
V
PP
. A single-word read can be used to access register information. During asynchronous reads, the
address is latched on the rising edge of ADV#.
Upon completion of reading the array, the device automatically enters an Automatic Power Savings
(APS) mode. APS mode consumes power comparable to standby mode.
4.1.2
Synchronous Mode
The 1.8 Volt Intel
Wireless Flash Memory supports synchronous reads. A synchronous read is
executed by implementing a read operation with the use of the CLK signal. During a synchronous
read operation, the CLK signal edge (rising or falling) controls flash array access.
A burst-mode read is synchronized to the CLK signal and outputs a 4-, 8- or continuous-word data
stream based on configuration register settings. However, by manipulating certain control signals,
the device can be made to output less then 4-, 8- or continuous-words.
相關(guān)PDF資料
PDF描述
28F320B3 SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
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