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參數(shù)資料
| 型號： | 28F400BX-TB |
| 廠商： | Intel Corp. |
| 英文描述： | 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 4兆位（256 × 16，為512k × 8）啟動塊閃存系列 |
| 文件頁數(shù)： | 15/49頁 |
| 文件大?。?/td> | 427K |
| 代理商： | 28F400BX-TB |
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E
SMART 3 ADVANCED BOOT BLOCK
–WORD-WIDE
15
PRELIMINARY
3.1.1
READ
The flash memory has three read modes available:
read array, read identifier, and read status. These
modes are accessible independent of the V
voltage. The appropriate read mode command must
be issued to the CUI to enter the corresponding
mode. Upon initial device power-up or after exit
from
deep
power-down
automatically defaults to read array mode.
mode,
the
device
CE# and OE# must be driven active to obtain data
at the outputs. CE# is the device selection control;
when active it enables the flash memory device.
OE# is the data output (DQ
0
–DQ
15
) control and it
drives the selected memory data onto the I/O bus.
For all read modes, WE# and RP# must be at V
IH
.
Figure 15 illustrates a read cycle.
3.1.2
OUTPUT DISABLE
With OE# at a logic-high level (V
), the device
outputs are disabled. Output pins DQ
0
–DQ
15
are
placed in a high-impedance state.
3.1.3
STANDBY
Deselecting the device by bringing CE# to a logic-
high level (V
) places the device in standby mode,
which
substantially
reduces
consumption. In standby, outputs DQ
0
–DQ
15
are
placed in a high-impedance state independent of
OE#. If deselected during program or erase
operation, the device continues to consume active
power until the program or erase operation is
complete.
device
power
3.1.4
DEEP POWER-DOWN / RESET
RP# at V
IL
initiates the deep power-down mode,
sometimes referred to as reset mode.
From read mode, RP# going low for time t
PLPH
accomplishes the following:
1.
deselects the memory
2.
places output drivers in a high-impedance
state
After return from power-down, a time t
PHQV
is
required until the initial memory access outputs are
valid. A delay
(t
PHWL
or t
PHEL
) is required after
return from power-down before a write sequence
can be initiated. After this wake-up interval, normal
operation is restored. The CUI resets to read array
mode, and the status register is set to 80H (ready).
If RP# is taken low for time t
PLPH
during a program
or erase operation, the operation will be aborted
and the memory contents at the aborted location
are no longer valid. After returning from an aborted
operation, time t
PHQV
or t
PHWL
/t
PHEL
must be met
before a read or write operation is initiated
respectively.
3.1.5
WRITE
A write is any command that alters the contents of
the memory array. There are two write commands:
Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User
Interface (CUI) initiates a sequence of internally-
timed functions that culminate in the completion of
the requested task (unless that operation is aborted
by either RP# being driven to V
IL
for t
PLRH
or an
appropriate suspend command).
The Command User Interface does not occupy an
addressable memory location. Instead, commands
are
written
into
the
microprocessor write timings when WE# and CE#
are low, OE# = V
IH
, and the proper address and
data (command) are presented. The command is
latched on the rising edge of the first WE# or CE#
pulse, whichever occurs first. Figure 16 illustrates a
write operation.
CUI
using
standard
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the
available commands. Appendix B provides detailed
information on moving between the different modes
of operation.
3.2
Modes of Operation
The flash memory has three read modes and two
write modes. The read modes are read array, read
identifier, and read status. The write modes are
program and block erase. Three additional modes
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