參數(shù)資料
型號： 21928
英文描述： Low-Frequency, Spread-Spectrum EconOscillator
中文描述： 的AMD - K6 - 2E處理器數(shù)據(jù)手冊3DNow！？技術(shù)手冊
文件頁數(shù)： 66/72頁
文件大小： 845K
代理商： 21928
56
3DNow! Instruction Set
Chapter 2
3DNow! Technology Manual
21928G/0—March 2000
PREFETCH/PREFETCHW
mnemonic
opcode
description
PREFETCH(W) mem8
0F 0Dh
Prefetch processor cache line into L1 data cache
(Dcache)
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
none
none
none
none
The PREFETCH instruction loads a processor cache line into the data cache. The
address of this line is specified by the mem8 value. For the AMD processor, the line
size is 32 bytes. In all future processors, the size of the line that is loaded by the
PREFETCH instruction will be at least 32-bytes. The PREFETCH instruction loads a
cache line even if the mem8 address is not aligned with the start of the line (although
some implementations, including the AMD-K6 family of processors, may perform the
cache fill starting from the cache miss or mem8 address). If a cache hit occurs (the
line is already in the Dcache) or a memory fault is detected, no bus cycle is initiated
and the instruction is treated as a NOP.
In applications where a large number of data sets must be processed, the PREFETCH
instruction can pre-load the next data set into the Dcache while, simultaneously, the
processor is operating on the present set of data. This instruction allows the
programmer to explicitly code operation concurrency. When the present set of data
values is completed, the next set is already available in the Dcache. An example of a
concurrent operation is vertices processing in 3D transformations, where the next set
of vertices can be prefetched into the data cache while the present set is being
transformed.
The PREFETCH instruction format in the processor is defined to allow extensions in
future AMD K86
processors. The instruction mnemonic for the PREFETCH
instruction includes the modR/M byte. Only the memory form of modR/M is valid (use
of the register form results in an invalid opcode exception). Because there is no
destination register, the three destination register field bits of the modR/M byte are
used to define the type of prefetch to be performed. The PREFETCH and
PREFETCHW instructions are defined by the bit pattern 000b and 001b, respectively.
All other bit patterns are reserved for future use.
The PREFETCHW instruction loads the prefetched line and sets the cache line MESI
state to modified (in anticipation of subsequent data writes to the line), unlike the
PREFETCH instruction, which typically sets the state to exclusive. If the data that is
prefetched into the Dcache is to be modified, use of the PREFETCHW instruction
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
219-2-8235-1 制造商:Airpax 功能描述:CIRCUIT PROTECTOR HYD MAGNETIC 制造商:Airpax 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:Sensata Technologies 功能描述:219-2-8235-1 /Pole # 2 /Prod Family: 0209
219-2-8696-1 制造商:Airpax 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:Sensata Technologies 功能描述:219-2-8696-1 /Pole # 2 /Prod Family: 0209
21-9290 制造商:Tenma 功能描述:Soldering Iron Pencil 25W 制造商:TENMA 功能描述:PENCIL SOLDERING IRON 25 WATT
219-2-9344-1 制造商:Airpax 功能描述:CIRCUIT PROTECTOR HYD MAGNETIC 制造商:Sensata Technologies 功能描述:219-2-9344-1 /Pole # 2 /Prod Family: 0209
21-9295 制造商:Tenma 功能描述:Soldering Iron Pencil 45W 制造商:TENMA 功能描述:PENCIL SOLDERING IRON 40 WATT
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