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參數資料
| 型號： | 21928 |
| 英文描述： | Low-Frequency, Spread-Spectrum EconOscillator |
| 中文描述： | 的AMD - K6 - 2E處理器數據手冊3DNow??？技術手冊 |
| 文件頁數： | 61/72頁 |
| 文件大?。?/td> | 845K |
| 代理商： | 21928 |
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Chapter 2
3DNow! Instruction Set
51
21928G/0—March 2000
3DNow! Technology Manual
PFSUBR
mnemonic
opcode/imm8
description
PFSUBR mmreg1, mmreg2/mem64
0Fh 0Fh / AAh
Packed floating-point reverse subtraction
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
none
MMX
none
PFSUBR is a vector instruction that performs subtraction of the destination operand
from the source operand. Both operands are single-precision, floating-point operands
with 24-bit significands. Table 20 on page 52 shows the numerical range of the
PFSUBR instruction.
The PFSUBR instruction performs the following operations:
mmreg1[31:0] = mmreg2/mem64[31:0] – mmreg1[31:0]
mmreg1[63:32] = mmreg2/mem64[63:32] – mmreg1[63:32]
Exception
Invalid opcode (6)
Device not available (7)
Real
X
X
Virtual
8086
X
X
Protected Description
X
X
The emulate instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1.
(In Protected Mode, CPL = 3.)
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