參數(shù)資料
型號: 21928
英文描述: Low-Frequency, Spread-Spectrum EconOscillator
中文描述: 的AMD - K6 - 2E處理器數(shù)據(jù)手冊3DNow???技術(shù)手冊
文件頁數(shù): 18/72頁
文件大?。?/td> 845K
代理商: 21928
8
3DNow! Technology
Chapter 1
3DNow! Technology Manual
21928G/0—March 2000
3DNow! Instruction Formats
The format of 3DNow! instruction encodings is based on the
conventional x86 modR/M instruction format and is similar to
the format used by MMX instructions. The assembly language
syntax used for the 3DNow! instructions is as follows:
3DNow! Mnemonic
mmreg1, mmreg2/mem64
The destination and source1 operand (mmreg1) must be an
MMX register (mm0–mm7). The source2 operand
(mmreg2/mem64) can be either an MMX register or a 64-bit
memory value.
The encoding uses the opcode prefix 0Fh followed by a second
opcode byte of 0Fh. To differentiate the various 3DNow!
instructions, a third instruction suffix byte is used. This suffix
byte occupies the same position at the end of a 3DNow!
instructions as would an imm8 byte. The opcode format is as
follows:
0Fh 0Fh modR/M [sib] [displacement]
3DNow!_suffix
The specific operands (mmreg1 and mmreg2/mem64)
determine the values used in modR/M [sib] [displacement], and
follow conventional x86 encodings. The 3DNow! suffix is
determined by the actual 3DNow! instruction. The 3DNow!
suffixes are defined in Table 2 on page 14.
As an example, the 3DNow! PFMUL instruction can produce
the following opcodes, depending on its use:
Opcode
Instruction
0F 0F CA B4
0F 0F 0B B4
0F 0F 4B 0A B4
26 0F 0F 0B B4
0F 0F 4C 83 0A B4
PFMUL mm1, mm2
PFMUL
mm1, [ebx]
PFMUL mm1, [ebx+10]
PFMUL
mm1, es:[ebx]
PFMUL mm1, [ebx+eax*4+10]
The encoding of the two performance-enhancement
instructions (FEMMS and PREFETCH) uses a single opcode
prefix 0Fh. The details of the opcodes for these instructions are
shown on pages 18 and 56 respectively.
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