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| 型號： | 21928 |
| 英文描述： | Low-Frequency, Spread-Spectrum EconOscillator |
| 中文描述： | 的AMD - K6 - 2E處理器數(shù)據(jù)手冊3DNow！？技術(shù)手冊 |
| 文件頁數(shù)： | 25/72頁 |
| 文件大小： | 845K |
| 代理商： | 21928 |
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Chapter 1
3DNow! Technology
15
21928G/0—March 2000
3DNow! Technology Manual
Task Switching
With respect to task switching, treat the 3DNow! instructions
exactly the same as MMX instructions. Operating system design
must be taken into account when writing a 3DNow! program.
The programmer must know whether the operating system
automatically saves the current states when task switching, or if
the 3DNow! program has to provide the code to save states.
If a task switch occurs, the Control Register (CR0) Task Switch
(TS) bit is set to 1. The processor then generates an interrupt 7
(int 7—Device Not Available) when it encounters the next
floating-point, 3DNow!, or MMX instruction, allowing the
operating system to save the state of the 3DNow!/MMX/FP
registers.
In a multitasking operating system, if there is a task switch
when 3DNow!/MMX applications are running with older
applications that do not include MMX instructions, the
MMX/FP register state is still saved automatically through the
int 7 handler.
Exceptions
Table 4 contains a list of exceptions that 3DNow! and MMX
instructions can generate.
Table 4.
3DNow! and MMX Instruction Exceptions
Virtual
8086
Invalid opcode (6)
X
Device not available (7)
X
Exception
Real
Protected
X
X
Description
X
X
The emulate instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1. (In
Protected Mode, CPL = 3.)
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