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參數資料
| 型號： | 21928 |
| 英文描述： | Low-Frequency, Spread-Spectrum EconOscillator |
| 中文描述： | 的AMD - K6 - 2E處理器數據手冊3DNow?。考夹g手冊 |
| 文件頁數： | 57/72頁 |
| 文件大?。?/td> | 845K |
| 代理商： | 21928 |
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Chapter 2
3DNow! Instruction Set
47
21928G/0—March 2000
3DNow! Technology Manual
PFRSQRT
mnemonic
opcode/imm8
description
PFRSQRT mmreg1, mmreg2/mem64
0Fh 0Fh / 97h
Floating-point reciprocal square root approximation
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
none
MMX
none
PFRSQRT is a scalar instruction that returns a low-precision estimate of the
reciprocal square root of the source operand. The single result value is duplicated in
both high and low halves of this instruction’s 64-bit result. The source operand is
single-precision with a 24-bit significand, and the result is accurate to 15 bits.
Negative operands are treated as positive operands for purposes of reciprocal square
root computation, with the sign of the result the same as the sign of the source
operand. Table 18 on page 48 shows the numerical range of the PFRSQRT instruction.
Increased accuracy (the full 24 bits of a single-precision significand) requires the use
of two additional instructions (PFRSQIT1 and PFRCPIT2). The first stage of this
increase or refinement in accuracy (PFRSQIT1) requires that the input and squared
output of the already executed PFRSQRT instruction be used as input to the
PFRSQIT1 instruction. Refer to “Division and Square Root” on page 59 for an
application-specific example of how to use this instruction and related instructions.
Exception
Invalid opcode (6)
Device not available (7)
Real
X
X
Virtual
8086
X
X
Protected Description
X
X
The emulate instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1.
(In Protected Mode, CPL = 3.)
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