參數(shù)資料
型號(hào): 21928
英文描述: Low-Frequency, Spread-Spectrum EconOscillator
中文描述: 的AMD - K6 - 2E處理器數(shù)據(jù)手冊(cè)3DNow!?技術(shù)手冊(cè)
文件頁(yè)數(shù): 53/72頁(yè)
文件大?。?/td> 845K
代理商: 21928
Chapter 2
3DNow! Instruction Set
43
21928G/0—March 2000
3DNow! Technology Manual
PFRCPIT2
mnemonic
opcode/imm8
description
PFRCPIT2 mmreg1, mmreg2/mem64
0Fh 0Fh / B6h
Packed floating-point reciprocal/reciprocal square
root, second iteration step
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
none
MMX
none
PFRCPIT2 is a vector instruction that performs the second and final intermediate
step in the Newton-Raphson iteration to refine the reciprocal or reciprocal square root
approximation produced by the PFRCP and PFSQRT instructions, respectively.
Table 16 on page 44 shows the numerical range of the PFRCPIT2 instruction.
The behavior of this instruction is only defined for those combinations of operands
such that the first source operand (mmreg1) was the output of either the PFRCPIT1 or
PFRSQIT1 instructions and the second source operand (mmreg2/mem64) was the
output of either the PFRCP or PFRSQRT instructions. Refer to
“Division and Square
Root” on page 59 for an application-specific example of how to use this instruction
and related instructions.
Exception
Invalid opcode (6)
Device not available (7)
Real
X
X
Virtual
8086
X
X
Protected Description
X
X
The emulate instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1.
(In Protected Mode, CPL = 3.)
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