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參數(shù)資料
| 型號(hào)： | 21928 |
| 英文描述： | Low-Frequency, Spread-Spectrum EconOscillator |
| 中文描述： | 的AMD - K6 - 2E處理器數(shù)據(jù)手冊(cè)3DNow！？技術(shù)手冊(cè) |
| 文件頁(yè)數(shù)： | 14/72頁(yè) |
| 文件大小： | 845K |
| 代理商： | 21928 |
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4
3DNow! Technology
Chapter 1
3DNow! Technology Manual
21928G/0—March 2000
The next step is for the programmer to determine if the 3DNow!
instructions are supported. Extended function 8000_0001h of
the CPUID instruction provides this information by returning
the extended feature bits in the EDX register. If bit 31 in the
EDX register is set to 1, 3DNow! instructions are supported. The
following code sample shows how to test for 3DNow! instruction
support.
mov
CPUID
test
jnz
eax, 80000001h
; setup ext. function 8000_0001h
; call the function
; test bit 31
; 3DNow! technology supported
edx, 80000000h
YES_3DNow!
The
Concatenating the code examples above will produce the basis
for a CPU detection software routine. A more comprehensive
code example is available on the AMD website at
http://www.amd.com/products/cpg/bin/.
processor
supports
all
of
the
above
features.
Register Set
The complete multimedia units in the processor combine the
existing MMX instructions with the new 3DNow! instructions.
In addition, by merging 3DNow! with MMX, it becomes possible
to write x86 programs containing both integer, MMX, and
floating-point graphics instructions with no performance
penalty for switching between the multimedia (integer) and
3DNow! (floating-point) units.
The processor implements eight 64-bit 3DNow!/MMX registers.
These registers are mapped onto the floating-point registers. As
shown in Figure 1, the 3DNow! and MMX instructions refer to
these registers as mm0 to mm7. Mapping the new 3DNow!/MMX
registers onto the floating-point register stack enables
backwards compatibility for the register saving that must occur
as a result of task switching.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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