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參數(shù)資料
| 型號(hào)： | 21928 |
| 英文描述： | Low-Frequency, Spread-Spectrum EconOscillator |
| 中文描述： | 的AMD - K6 - 2E處理器數(shù)據(jù)手冊(cè)3DNow?。考夹g(shù)手冊(cè) |
| 文件頁數(shù)： | 64/72頁 |
| 文件大?。?/td> | 845K |
| 代理商： | 21928 |
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54
3DNow! Instruction Set
Chapter 2
3DNow! Technology Manual
21928G/0—March 2000
PMULHRW
mnemonic
opcode/imm8
description
PMULHRW mmreg1, mmreg2/mem64
0F 0Fh/B7h
Multiply signed packed 16-bit values with rounding
and store the high 16 bits.
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
None
MMX
None
The PMULHRW instruction multiplies the four signed 16-bit integer values in the
source operand (an MMX register or a 64-bit memory location) by the four
corresponding signed 16-bit integer values in the destination operand (an MMX
register). The PMULHRW instruction then adds 8000h to the lower 16 bits of the
32-bit result, which results in the rounding of the high-order, 16-bit result. The
high-order 16 bits of the result (including the sign bit) are stored in the destination
operand.
The PMULHRW instruction provides a numerically more accurate result than the
PMULMH instruction, which truncates the result instead of rounding.
Exception
Invalid opcode (6)
Device not available (7)
Real
X
X
Virtual
8086
X
X
Protected Description
X
X
The emulate instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1.
(In Protected Mode, CPL = 3.)
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| 21A | Low-Frequency Dual EconOscillator |
| 21B | Low-Frequency Dual EconOscillator |
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參數(shù)描述 |
|---|---|
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