參數(shù)資料
型號: 21928
英文描述: Low-Frequency, Spread-Spectrum EconOscillator
中文描述: 的AMD - K6 - 2E處理器數(shù)據(jù)手冊3DNow?。考夹g(shù)手冊
文件頁數(shù): 24/72頁
文件大?。?/td> 845K
代理商: 21928
14
3DNow! Technology
Chapter 1
3DNow! Technology Manual
21928G/0—March 2000
Table 2.
3DNow! Floating-Point Instructions
Operation
Function
Opcode
Suffix
BFh
9Eh
9Ah
AAh
AEh
90h
A0h
B0h
94h
A4h
0Dh
1Dh
96h
97h
B4h
A6h
A7h
B6h
B7h
PAVGUSB
PFADD
PFSUB
PFSUBR
PFACC
PFCMPGE
PFCMPGT
PFCMPEQ
PFMIN
PFMAX
PI2FD
PF2ID
PFRCP
PFRSQRT
PFMUL
PFRCPIT1
PFRSQIT1
PFRCPIT2
PMULHRW
Packed 8-bit Unsigned Integer Averaging
Packed Floating-Point Addition
Packed Floating-Point Subtraction
Packed Floating-Point Reverse Subtraction
Packed Floating-Point Accumulate
Packed Floating-Point Comparison, Greater or Equal
Packed Floating-Point Comparison, Greater
Packed Floating-Point Comparison, Equal
Packed Floating-Point Minimum
Packed Floating-Point Maximum
Packed 32-bit Integer to Floating-Point Conversion
Packed Floating-Point to 32-bit Integer
Packed Floating-Point Reciprocal Approximation
Packed Floating-Point Reciprocal Square Root Approximation
Packed Floating-Point Multiplication
Packed Floating-Point Reciprocal First Iteration Step
Packed Floating-Point Reciprocal Square Root First Iteration Step
Packed Floating-Point Reciprocal/Reciprocal Square Root Second Iteration Step
Packed 16-bit Integer Multiply with rounding
Table 3.
3DNow! Performance-Enhancement Instructions
Operation
Function
Opcode
Second Byte
0Eh
0Dh
FEMMS
PREFETCH/PREFETCHW *
Note:
* The AMD-K6-2 and AMD-K6-
III
processors execute the PREFETCHW instruction identically to the PREFETCH instruction.
On the AMD Athlon processor, PREFETCHW can increase performance by providing a hint to the processor of an intent to
modify the cache line.
Faster entry/exit of the MMX
or floating-point state
Prefetch at least a 32-byte line into L1 data cache (Dcache)
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