
PIC16F87XA
DS39582A-page 80
Advance Information
2001 Microchip Technology Inc.
REGISTER 9-4:
SSPCON: MSSP CONTROL REGISTER1 (I
2
C MODE) (ADDRESS 14h)
R/W-0
WCOL
bit 7
R/W-0
SSPOV
R/W-0
SSPEN
R/W-0
CKP
R/W-0
SSPM3
R/W-0
SSPM2
R/W-0
SSPM1
R/W-0
SSPM0
bit 0
bit 7
WCOL:
Write Collision Detect bit
In Master Transmit mode:
1
= A write to the SSPBUF register was attempted while the I
2
C conditions were not valid for a
transmission to be started. (Must be cleared in software.)
0
= No collision
In Slave Transmit mode:
1
= The SSPBUF register is written while it is still transmitting the previous word. (Must be cleared
in software.)
0
= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
SSPOV:
Receive Overflow Indicator bit
In Receive mode:
1
=A byte is received while the SSPBUF register is still holding the previous byte. (Must be
cleared in software.)
0
= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
SSPEN:
Synchronous Serial Port Enable bit
1
= Enables the serial port and configures the SDA and SCL pins as the serial port pins
0
= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, the SDA and SCL pins must be properly configured as input or output.
CKP:
SCK Release Control bit
In Slave mode:
1
= Release clock
0
= Holds clock low (clock stretch). (Used to ensure data setup time.)
In Master mode:
Unused in this mode
SSPM3:SSPM0:
Synchronous Serial Port Mode Select bits
1111
= I
2
C Slave mode, 10-bit address with START and STOP bit interrupts enabled
1110
= I
2
C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1011
= I
2
C Firmware Controlled Master mode (Slave IDLE)
1000
= I
2
C Master mode, clock = F
OSC
/ (4 * (SSPADD+1))
0111
= I
2
C Slave mode, 10-bit address
0110
= I
2
C Slave mode, 7-bit address
Note:
Bit combinations not specifically listed here are either reserved, or implemented in
SPI mode only.
bit 6
bit 5
bit 4
bit 3-0
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
x = Bit is unknown