
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 21
PIC16F87XA
2.2.2.2
OPTION_REG Register
The OPTION_REG Register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
OPTION_REG REGISTER (ADDRESS 81h, 181h)
Note:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1
RBPU
bit 7
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
bit 0
bit 7
RBPU:
PORTB Pull-up Enable bit
1
= PORTB pull-ups are disabled
0
= PORTB pull-ups are enabled by individual port latch values
INTEDG
: Interrupt Edge Select bit
1
= Interrupt on rising edge of RB0/INT pin
0
= Interrupt on falling edge of RB0/INT pin
T0CS
: TMR0 Clock Source Select bit
1
= Transition on RA4/T0CKI pin
0
= Internal instruction cycle clock (CLKOUT)
T0SE
: TMR0 Source Edge Select bit
1
= Increment on high-to-low transition on RA4/T0CKI pin
0
= Increment on low-to-high transition on RA4/T0CKI pin
PSA
: Prescaler Assignment bit
1
= Prescaler is assigned to the WDT
0
= Prescaler is assigned to the Timer0 module
PS2:PS0
: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
x = Bit is unknown
Note:
When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are
enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3
and ensure the proper operation of the device
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128