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參數(shù)資料
| 型號： | 16F876A |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 28/40-pin Enhanced FLASH Microcontrollers |
| 中文描述： | 28/40-pin增強(qiáng)閃存微控制器 |
| 文件頁數(shù)： | 105/222頁 |
| 文件大?。?/td> | 4013K |
| 代理商： | 16F876A |
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2001 Microchip Technology Inc.
Advance Information
DS39582A-page 103
PIC16F87XA
9.4.14
SLEEP OPERATION
While in SLEEP mode, the I
2
C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
9.4.15
EFFECT OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
9.4.16
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I
2
C
bus may be taken when the P bit (SSPSTAT<4>) is set,
or the bus is IDLE, with both the S and P bits clear.
When the bus is busy, enabling the SSP Interrupt will
generate the interrupt when the STOP condition
occurs.
In multi-master operation, the SDA line must be moni-
tored for arbitration, to see if the signal level is at the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
Address Transfer
Data Transfer
A START Condition
A Repeated START Condition
An Acknowledge Condition
9.4.17
MULTI -MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I
2
C port to its IDLE state (Figure 9-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I
2
C bus is free, the user can resume communication by
asserting a START condition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I
2
C bus is free, the user can resume communication
by asserting a START condition.
The Master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I
2
C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is IDLE and the S and P bits are
cleared.
FIGURE 9-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
by master
SDA line pulled low
by another source
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master. Bus collision has occurred.
Set bus collision
interrupt (BCLIF).
Data changes
while SCL = 0
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