
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 19
PIC16F87XA
Bank 2
100h
(3)
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
Timer0 Module Register
Program Counter
’
s (PC) Least Significant Byte
IRP
RP1
RP0
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
EEPROM Data Register Low Byte
EEPROM Address Register Low Byte
—
—
EEPROM Data Register High Byte
—
—
—
—
(5)
0000 0000
29, 148
101h
102h
(3)
103h
(3)
104h
(3)
105h
106h
107h
108h
109h
10Ah
(1,3)
PCLATH
10Bh
(3)
10Ch
10Dh
10Eh
10Fh
Bank 3
180h
(3)
TMR0
PCL
STATUS
FSR
xxxx xxxx
53, 148
0000 0000
28, 148
0001 1xxx
20, 148
xxxx xxxx
29, 148
—
xxxx xxxx
43, 148
—
—
—
---0 0000
28, 148
0000 000x
22, 148
xxxx xxxx
37, 149
xxxx xxxx
37, 149
--xx xxxx
37, 149
---- xxxx
37, 149
TO
PD
Z
DC
C
—
—
PORTB
—
—
—
—
—
—
INTCON
EEDATA
EEADR
EEDATH
EEADRH
RBIE
TMR0IF
INTF
RBIF
EEPROM Address Register High Byte
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
RBPU
INTEDG
T0CS
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
EEPGD
—
—
—
EEPROM Control Register2 (not a physical register)
Reserved maintain clear
Reserved maintain clear
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as
‘
0
’
.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2:
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3:
These registers can be addressed from any bank.
4:
PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as
‘
0
’
.
5:
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
0000 0000
29, 148
181h
182h
(3)
183h
(3)
184h
(3)
185h
186h
187h
188h
189h
18Ah
(1,3)
PCLATH
18Bh
(3)
18Ch
18Dh
18Eh
18Fh
Legend:
OPTION_REG
PCL
STATUS
FSR
—
TRISB
—
—
—
T0SE
PSA
PS2
PS1
PS0
1111 1111
21, 148
0000 0000
28, 148
0001 1xxx
20, 148
xxxx xxxx
29, 148
—
1111 1111
43, 148
—
—
—
---0 0000
28, 148
0000 000x
22, 148
x--- x000
32, 149
---- ----
37, 149
0000 0000
0000 0000
TO
PD
Z
DC
C
—
—
—
—
INTCON
EECON1
EECON2
RBIE
WRERR
TMR0IF
WREN
INTF
WR
RBIF
RD
—
—
—
—
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Details
on
page: