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| 型號(hào)： | 16F876A |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 28/40-pin Enhanced FLASH Microcontrollers |
| 中文描述： | 28/40-pin增強(qiáng)閃存微控制器 |
| 文件頁(yè)數(shù)： | 104/222頁(yè) |
| 文件大?。?/td> | 4013K |
| 代理商： | 16F876A |
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PIC16F87XA
DS39582A-page 102
Advance Information
2001 Microchip Technology Inc.
9.4.12
ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge
sequence
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
is presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (T
BRG
) and
the SCL pin is de-asserted (pulled high). When the SCL
pin is sampled high (clock arbitration), the baud rate
generator counts for T
BRG
. The SCL pin is then pulled
low. Following this, the ACKEN bit is automatically
cleared, the baud rate generator is turned off and the
MSSP module then goes into IDLE mode (Figure 9-23).
enable
bit,
ACKEN
9.4.12.1
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
9.4.13
STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit, by setting the STOP sequence enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one T
BRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
T
BRG
later, the PEN bit is cleared and the SSPIF bit is
set (Figure 9-24).
9.4.13.1
WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 9-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Note:
T
BRG
= one baud rate generator period.
SDA
SCL
Set SSPIF at the end
of receive
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
Cleared in
software
T
BRG
T
BRG
ACK
8
D0
9
SSPIF
Set SSPIF at the end
of Acknowledge sequence
Cleared in
software
SCL
SDA
SDA asserted low before rising edge of clock
to setup STOP condition
.
Write to SSPCON2
Set PEN
Falling edge of
9th clock
SCL = 1 for T
BRG
, followed by SDA = 1 for T
BRG
after SDA sampled high. P bit (SSPSTAT<4>) is set
SCL brought high after T
BRG
Note:
T
BRG
= one baud rate generator period.
T
BRG
T
BRG
T
BRG
ACK
P
T
BRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
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