
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 17
PIC16F87XA
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Details
on
page:
Bank 0
00h
(3)
01h
02h
(3)
03h
(3)
04h
(3)
05h
06h
07h
08h
(4)
09h
(4)
0Ah
(1,3)
0Bh
(3)
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
Indirect Data Memory Address Pointer
—
—
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
—
—
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
TMR0IE
INTE
PSPIF
(3)
ADIF
RCIF
TXIF
—
CMIF
—
EEIF
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
—
—
T1CKPS1 T1CKPS0 T1OSCEN
Timer2 Module Register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
CKP
0000 0000
29, 148
xxxx xxxx
53, 148
0000 0000
28, 148
0001 1xxx
20, 148
xxxx xxxx
29, 148
--0x 0000
41, 148
xxxx xxxx
43, 148
xxxx xxxx
45, 148
xxxx xxxx
46, 148
---- -xxx
47, 148
---0 0000
28, 148
0000 000x
22, 148
0000 0000
24, 148
-0-0 0--0
26, 148
xxxx xxxx
58, 148
xxxx xxxx
58, 148
PD
Z
DC
C
—
RE2
RE1
RE0
RBIE
SSPIF
BCLIF
TMR0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
TMR1IF
CCP2IF
T1SYNC
TMR1CS TMR1ON
--00 0000
55, 148
0000 0000
60, 148
TMR2ON
T2CKPS1 T2CKPS0
-000 0000
59, 148
xxxx xxxx
77, 148
0000 0000
SSPM3
SSPM2
SSPM1
SSPM0
71, 80,
148
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as
‘
0
’
.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2:
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
3:
These registers can be addressed from any bank.
4:
PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as
‘
0
’
.
5:
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
—
—
SPEN
RX9
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
A/D Result Register High Byte
ADCS1
ADCS0
xxxx xxxx
61, 148
xxxx xxxx
61, 148
CCP1X
SREN
CCP1Y
CREN
CCP1M3
ADDEN
CCP1M2
FERR
CCP1M1
OERR
CCP1M0
--00 0000
62, 148
RX9D
0000 000x
110, 148
0000 0000
116, 148
0000 0000
116, 148
xxxx xxxx
61, 148
xxxx xxxx
61, 148
CCP2M0
--00 0000
62, 148
xxxx xxxx
131, 148
ADON
0000 00-0
125, 148
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CHS2
CHS1
CHS0
GO/DONE
—