
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 77
PIC16F87XA
9.3.8
SLEEP OPERATION
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP inter-
rupt flag bit will be set and if enabled, will wake the
device from SLEEP.
9.3.9
EFFECTS OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
9.3.10
BUS MODE COMPATIBILITY
Table 9-1 shows the compatibility between the stan-
dard SPI modes and the states the CKP and CKE con-
trol bits.
TABLE 9-1:
SPI BUS MODES
There is also a SMP bit which controls when the data is
sampled.
TABLE 9-2:
REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
INTCON
GIE/GIEH
PEIE/
GIEL
ADIF
ADIE
ADIP
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PIE1
IPR1
TRISC
SSPBUF
SSPCON
TRISA
PSPIF
(1)
PSPIE
(1)
PSPIP
(1)
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
—
PORTA Data Direction Register
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF
CCP1IE
CCP1IP
TMR2IF
TMR2IE
TMR2IP
TMR1IF
TMR1IE
TMR1IP
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
--11 1111 --11 1111
SSPSTAT
Legend:
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
x = unknown, u = unchanged,
-
= unimplemented read as '0'.
Shaded cells are not used by the MSSP in SPI mode.
The PSPIF, PSPIE and PSPIP bits are reserved on 28-pin devices. Always maintain these bits clear.
Note
1: