
PIC16F870/871
DS30569A-page 96
Preliminary
1999 Microchip Technology Inc.
TABLE 11-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Devices
Power-on Reset,
Brown-out Reset
870
871
xxxx xxxx
870
871
N/A
870
871
xxxx xxxx
870
871
0000h
870
871
0001 1xxx
870
871
xxxx xxxx
870
871
--0x 0000
870
871
xxxx xxxx
870
871
xxxx xxxx
870
871
xxxx xxxx
870
871
---- -xxx
870
871
---0 0000
870
871
0000 000x
870
871
r000 -000
870
871
0000 -000
870
871
---0 ----
870
871
xxxx xxxx
870
871
xxxx xxxx
870
871
--00 0000
870
871
0000 0000
870
871
-000 0000
870
871
xxxx xxxx
870
871
xxxx xxxx
870
871
--00 0000
870
871
0000 000x
870
871
0000 0000
870
871
0000 0000
870
871
xxxx xxxx
870
871
0000 00-0
870
871
1111 1111
870
871
--11 1111
870
871
1111 1111
870
871
1111 1111
870
871
1111 1111
870
871
0000 -111
870
871
r000 -000
870
871
0000 0000
870
871
---0 ----
870
871
---- --qq
870
871
1111 1111
870
871
0000 -010
870
871
0000 0000
870
871
xxxx xxxx
Legend:
u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as ’0’,
q
= value depends
on condition,
r
= reserved maintain clear.
Note 1:
One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the inter-
rupt vector (0004h).
3:
See Table 11-5 for reset value for specific condition.
MCLR Resets
WDT Reset
uuuu uuuu
N/A
uuuu uuuu
0000h
000q quuu
(3)
uuuu uuuu
--0u 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---0 0000
0000 000u
r000 -000
0000 -000
---0 ----
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 000x
0000 0000
0000 0000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 -000
0000 0000
---0 ----
---- --uu
1111 1111
0000 -010
0000 0000
uuuu uuuu
Wake-up via WDT or
Interrupt
uuuu uuuu
N/A
uuuu uuuu
PC + 1
(2)
uuuq quuu
(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---u uuuu
uuuu uuuu
(1)
ruuu -uuu
(1)
uuuu -uuu
(1)
---u ----
(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
ruuu -uuu
uuuu uuuu
---u ----
---- --uu
1111 1111
uuuu -uuu
uuuu uuuu
uuuu uuuu
W
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
ADRESH
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
PIE2
PCON
PR2
TXSTA
SPBRG
ADRESL